Memory test circuit which tests address access time of clock synchronized memory

1 . A memory test circuit for testing an access time of a clock synchronization type memory, comprising:

a delay circuit that generates a delayed clock obtained by delaying, by a time acceptable for a memory performance, a clock supplied to the memory;

a sampling circuit that takes in and outputs an output from the memory at a timing of the delayed clock from the delay circuit; and

a coincidence detection circuit that detects coincidence or non-coincidence by comparing an output from the sampling circuit with an expected value for the output from the memory.

2 . The memory test circuit according to claim 1 , wherein the delay circuit includes a plurality of primitive gates.

3 . The memory test circuit according to claim 1 ,

wherein the delay circuit and the sampling circuit comprises a first delay circuit and a first sampling circuit, respectively, the memory test circuit further comprising:

a second delay circuit that delays the clock to a greater extent than a delay of the first delay circuit; and

a second sampling circuit that takes in and outputs an output from the coincidence detection circuit at a timing of a delayed clock from the second delay circuit.

4 . The memory test circuit according to claim 1 , wherein:

the memory is capable of outputting parallel data; and

the sampling circuit and the coincidence detection circuit are provided in parallel by a number of bits outputted from the memory.

5 . The memory test circuit according to claim 4 ,

wherein the coincidence detection circuit, the delay circuit, and the sampling circuit comprises a first coincidence detection circuit, a first delay circuit, and a first sampling circuit, respectively, the memory test circuit further comprising:

a second coincidence detection circuit that receives an output from the first coincidence detection circuit;

a second delay circuit that delays the clock to a greater extent than a delay of the first delay circuit; and

a second sampling circuit that takes in and outputs an output from the second coincidence detection circuit at a timing of a delayed clock from the second delay circuit.

6 . A memory test device, comprising:

the memory test circuit according to claim 1 ; and

a memory BIST circuit that writes and reads test data into and out of the memory, and executes a memory test for comparing an output and the expected value for the output from the memory.

7 . A memory device, comprising:

the memory test device according to claim 6 ; and

a memory.

8 . The memory device according to claim 7 , further comprising a plurality of memories including the memory, wherein

the memory test circuit is shared by the plurality of memories.

9 . A memory test unit, comprising:

a built-in self test (BIST) circuit that provides an address data, an expected value and a clock signal, the address data and the clock signal being supplied to a clock synchronized memory; and

a memory speed evaluation circuit comprising:

a delay circuit which delays the clock signal to produce a delayed clock signal;

a latch circuit which latches an output from the memory based on the delayed clock signal; and

a coincidence circuit which compares an output of the latch circuit with the expected value.

10 . The memory test unit as claimed in claim 9 , further comprising:

a delay generator which delays the clock signal with a delay period larger than a delay period when the delay circuit delays the clock signal, in order to produce a second delayed clock signal; and

a sampling circuit which latches an output of the coincidence circuit based on the second delayed clock signal.

11 . The memory test unit as claimed in claim 9 , wherein the memory speed evaluation circuit is shared by a first pair of the BIST circuit and the memory and a second pair of the BIST circuit and the memory.

12 . A method of evaluating a memory speed, comprising;

delaying a clock signal produced in a BIST circuit to produce a delayed clock signal;

latching an output from a clock synchronized memory in response to the delayed clock signal; and

determining whether a latch output and an expected value are coincident.