Spin transfer MRAM device with separated CPP assisted writing
View Patent ↗A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When R MTJ1 >R MTJ2 , the bit cell has a “0” state, and when R MTJ1 <R MTJ2 , the bit cell has a “1” state.
1. A method of writing a “0” resistance state to a bit cell in a spin-transfer MRAM structure wherein the bit cell is comprised of two sub-cells each having a CPP cell formed above a MTJ cell and connected through a conductive spacer, each of said MTJ cells has a first free layer with near zero anisotropy, and each of said CPP cells has a second free layer with a substantial anisotropy and a top electrode contacting a bit line, and a first conductive spacer in first sub-cell and a second conductive spacer in a second sub-cell are connected through a transistor, comprising:
(a) injecting a write current into a first bit line contacting a top electrode in the CPP cell in the first sub-cell, said write current passes through the first CPP cell and into the first conductive spacer and then into the second conductive spacer and out through a second CPP cell to a second bit line contacting the top electrode in the second CPP cell to form a “0” resistance state in the first CPP cell, a “1” resistance state in the first MTJ cell, a “1” resistance state in the second CPP cell, and a “0” resistance state in the second MTJ cell; and
(b) simultaneously applying a current to a write word line that controls a voltage to said transistor and causes current to flow from the first conductive spacer to the second conductive spacer.
2. A method of writing a “1” resistance state to a bit cell in a spin-transfer MRAM structure wherein the bit cell is comprised of two sub-cells each having a CPP cell formed above a MTJ cell and connected through a conductive spacer, each of said MTJ cells has a first free layer with near zero anisotropy, and each of said CPP cells has a second free layer with a substantial anisotropy and a top electrode contacting a bit line, and a first conductive spacer in first sub-cell and a second conductive spacer in a second sub-cell are connected through a transistor, comprising:
(a) injecting a write current into a second bit line contacting a top electrode in the CPP cell in the second sub-cell, said write current passes through the second CPP cell and into the second conductive spacer and then into the first conductive spacer and out through a first CPP cell to a first bit line contacting the top electrode in the first sub-cell to form a “1” resistance state in the first CPP cell, a “0” resistance state in the first MTJ cell, a “0” resistance state in the second CPP cell, and a “1” resistance state in the second MTJ cell; and
(b) simultaneously applying a current to a write word line that controls a voltage to said transistor and causes current to flow from the second conductive spacer to the first conductive spacer.
3. A method of reading a resistance state of a bit cell in a spin-transfer MRAM structure wherein the bit cell is comprised of two sub-cells each having a CPP cell formed above a MTJ cell and connected through a conductive spacer, each of said MTJ cells has a first free layer with near zero anisotropy and is formed on a bottom electrode that is grounded through a read transistor wherein said read transistors are controlled by a read word line, and each of said CPP cells has a second free layer with a substantial anisotropy and a top electrode connected to a bit line, and a first conductive spacer in first sub-cell and a second conductive spacer in a second sub-cell are connected through a transistor, comprising:
(a) biasing a first bit line connected to a first CPP cell and biasing a second bit line connected to a second CPP cell with a certain voltage; and
(b) applying a current to said read word line that applies a voltage to said read transistors and enables a sense amplifier to detect the resistance state in the MTJ cell in each sub-cell.
4. The method of claim 3 wherein said certain voltage used for biasing the first bit line a second bit line is from about 0.05 to 0.5 volts.
5. The method of claim 3 wherein a “0” resistance state for the bit cell is detected when the resistance in the MTJ in the first sub-cell is greater than the resistance of the MTJ in the second sub-cell, and a “ 1 ,” resistance state for the bit cell is detected when the resistance in the MTJ in the second sub-cell is greater than the resistance of the MTJ in the first sub-cell.