Thin semiconductor device having embedded die support and methods of making the same
View Patent ↗Ultra-thin semiconductor devices, including piezoresistive sensing elements can be formed in a wafer stack that facilitates handling many thin device dice at a wafer level. Three embodiments are provided to form the thin dice in a wafer stack using three different fabrication techniques that include anodic bonding, adhesive bonding and fusion bonding. A trench is etched around each thin die to separate the thin die from others in the wafer stack. A tether layer, also known as a tether, is used to hold thin dice or dice in a wafer stack. Such as wafer stack holds many thin dice together at a wafer level for handling and enables easier die picking in packaging processes.
1. A wafer stack comprising:
a silicon device wafer and a silicon substrate wafer;
a silicon die having a circuit formed thereon, the die extending over a cavity in the device wafer and having an outer perimeter defined by a trench formed in the device wafer, the trench separating the die from the device wafer;
a die tether layer attached to the die, extending across the trench and ending on the device wafer; and
wherein the die tether layer is perforated.
2. The wafer stack of claim 1 , wherein the trench has a bottom and wherein the trench bottom is comprised of material of the die tether layer.
3. The wafer stack of claim 1 , wherein the circuit on the die forms part of pressure sensor.
4. The wafer stack of claim 1 , wherein the wafer stack is made of two silicon wafers attached to each other by a fusion bond, the trench separating the silicon die from the device wafer, and a single tether or a die tether layer attaching the silicon die to the device wafer.
5. A wafer stack comprising:
a thin silicon device layer having top and bottom surfaces and a cap wafer;
a die formed on a portion of the thin silicon device layer and having a circuit on the top surface of the die;
a tether covering at least a portion of the top surface of the die and extending over the die;
wherein the cap wafer is suspended over the die and forms a sealed gap, and wherein the die has an outer perimeter defined by a trench formed from the bottom surface of the thin silicon device layer and surrounding the die, the die being attached to the wafer stack by a passivation layer extending over the trench;
wherein said tether extends across the trench attaching the die to the wafer stack; and
wherein the cap wafer is comprised of a borosilicate glass.
6. The wafer stack of claim 5 , further including an anodic bonding between the cap wafer and top surface of the thin silicon layer.
7. The wafer stack of claim 6 , wherein the cap wafer is comprised of single crystalline silicon.
8. The wafer stack of claim 5 , wherein the trench has a bottom and wherein the trench bottom is comprised of material of the tether layer.
9. The wafer stack of claim 5 , wherein the tether layer is perforated.
10. The wafer stack of claim 5 , wherein the circuit forms part of a pressure sensor.
11. A wafer stack comprising:
a silicon device wafer and a silicon substrate wafer;
a silicon die formed from the silicon device wafer, the silicon die having first and second opposing surfaces bounded by an edge and a circuit formed on the first surface, the die extending over a cavity and having an outer perimeter surrounded by an open trench, the open trench being comprised of opposing first and second sides, the first side of the open trench being the edge of the silicon die, the open trench also have a bottom, which is comprised of a tether layer that is formed over and attached to at least a portion of the second surface of the die, the tether layer extending between the first and second opposing sides of the trench and supporting the silicon die;
wherein the tether layer is substantially planar and substantially parallel to at least the second surface of the die; and
wherein the tether layer is comprised of silicon dioxide.
12. A wafer stack comprising:
a silicon device wafer and a cap wafer;
a silicon die formed from the silicon device wafer, the silicon die having first and second opposing surfaces bounded by an edge and a circuit formed on the first surface, the die extending over a cavity and having an outer perimeter surrounded by an open trench, the open trench being comprised of opposing first and second sides, the first side of the open trench being the edge of the silicon die, the open trench also have a bottom, which is comprised of a tether layer that is formed over and attached to at least a portion of the first surface of the die, the tether layer extending between the first and second opposing sides of the trench and supporting the silicon die; and
a tether layer attached to and covering at least a portion of the first surface of the silicon die, the die tether layer extending between the first and second opposing sides of the trench and ending at the device wafer.
13. The wafer stack of claim 12 , wherein the tether layer is a passivation layer formed over at least part of the first surface of the silicon die.
14. The wafer stack of claim 13 , wherein the edge of the silicon die is uninterrupted around the silicon die and substantially uninterrupted between the tether layer and the second surface of the silicon die.