IP Library Granted Patent US 8,278,185
Granted Patent B2
US 8,278,185 · App. 12/473,307 · Granted Oct 2, 2012

Method for forming device isolation layer of semiconductor device and non-volatile memory device

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Quick Facts
Patent No.
US 8,278,185
App. No.
12/473,307
Granted
Oct 2, 2012
Kind
B2
Abstract

A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a second predetermined depth inside the trenches; forming a liner oxide layer having a predetermined thickness on internal walls of the trenches with the first insulation layer formed therein; and forming a second insulation layer for forming a device isolation layer over the substrate with the liner oxide layer formed therein, wherein the second insulation layer has a lower etch rate than that of the first insulation layer.

Claims (20)

1. A method for forming a device isolation layer of a non-volatile memory device, comprising:

forming a tunnel insulation layer, a charge storage layer, and a hard mask layer over a substrate;

forming trenches having a first depth by etching the hard mask layer, the charge storage layer, the tunnel insulation layer, and the substrate;

forming a first insulation layer having a second depth inside the trenches; and

forming a liner oxide layer having a given thickness on internal walls of the trenches, which are not covered by the first insulation layer, and on a surface of the first insulation layer through an oxidation process of the hard mask; and

forming a second insulation layer over the liner oxide layer,

wherein the second insulation layer has a lower etch rate than that of the first insulation layer.

2. The method of claim 1 , wherein the forming of the first insulation layer includes:

forming a flowable oxide layer over the hard mask layer with the trenches;

forming the first insulation layer by performing a thermal treatment;

planarizing the first insulation layer until a surface of the hard mask layer is exposed; and

removing the first insulation layer while leaving the first insulation layer in the second depth inside the trenches.

3. The method of claim 1 , wherein the forming of the liner oxide layer includes:

oxidizing internal walls of the trenches with the first insulation layer to form the liner oxide layer.

4. The method of claim 1 , wherein a surface of the first insulation layer is lower than a surface of the hard mask layer.

5. The method of claim 1 , wherein the predetermined thickness of the liner oxide layer is a thickness ranging from approximately 20 Å to approximately 150 Å.

6. The method of claim 1 , wherein the first insulation layer is an SOD layer formed of PSZ, and the second insulation layer is formed of HDP oxide.

7. The method of claim 1 , further comprising:

planarizing the second insulation layer until a surface of the hard mask layer is exposed after the forming of the second insulation layer; and

removing the hard mask layer.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE IS HYNIX SEMICONDUCTOR INC. NOT HYNIX-SEMICONDUCTOR INC. THERE IS NO HYPHEN IN THE NAME. PREVIOUSLY RECORDED ON REEL 67328 FRAME 814. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 14, 2024
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067412/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067369/0832 →
CHANGE OF NAME Recorded May 6, 2024
From: HYNIX-SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067328/0814 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 28, 2009
From: KOO, JAE-HYOUNG; KIM, JIN-WOONG; LEE, MI-RI; KIM, CHI-HO; BIN, JIN-HO
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 022743/0564 →