Bonded semiconductor structure and method of fabricating the same
View Patent ↗A method of forming a bonded semiconductor structure circuit includes providing a support substrate which carries a first semiconductor circuit and providing a first interconnect region carried by the support substrate. The method includes providing a bonded semiconductor substrate which is bonded to the first interconnect region through a bonding interface and forming a second semiconductor circuit which is carried by the first bonded semiconductor substrate.
1. A method of forming a bonded semiconductor structure circuit, comprising:
providing a support substrate which carries a first semiconductor circuit;
providing a first interconnect region carried by the support substrate, the first interconnect region including a conductive line connected to the first semiconductor circuit, wherein the conductive line includes a refractory metal;
providing a first bonded semiconductor substrate which is bonded to the first interconnect region through a first bonding interface;
forming a second semiconductor circuit which is carried by the first bonded semiconductor substrate;
forming a dielectric layer which is adjacent to a first sidewall of the first bonded semiconductor substrate;
forming a conductive line which extends through the dielectric layer; and
providing a second interconnect region which is carried by the first bonded semiconductor substrate, wherein the second interconnect region is connected to the second semiconductor circuit;
wherein the first and second semiconductor circuits are connected together through the first and second interconnect regions and the conductive line extending through the dielectric layer.
2. The method of claim 1 , wherein the first and second semiconductor circuits operate as volatile and non-volatile memory circuits, respectively.
3. The method of claim 1 , wherein the first and second semiconductor circuits operate as a memory circuit and control circuit, respectively.
4. The method of claim 1 , wherein the first semiconductor circuit includes a vertically oriented semiconductor device and the second semiconductor circuit includes a horizontally oriented semiconductor device.
5. The method of claim 1 , wherein the vertically oriented semiconductor device operates as a memory device and the second semiconductor circuit controls the operation of the vertically oriented semiconductor device.
6. The method of claim 4 , wherein the vertically oriented semiconductor device includes a layer structure which includes an oxide layer which extends between a silicon layer and a nitride layer.
7. The method of claim 1 , wherein the first bonded semiconductor includes crystalline semiconductor material.
8. The method of claim 1 , further including providing a second bonded semiconductor substrate which is bonded to the second interconnect region through a second bonding interface.
9. A method of forming a bonded semiconductor structure circuit, comprising:
providing a support substrate;
forming a vertically oriented semiconductor device which is carried by the support substrate;
forming a first interconnect region which is carried by the support substrate and includes a conductive line connected to the vertically oriented semiconductor device;
coupling a first bonded substrate to the first interconnect region through a bonding layer and bonding interface;
forming a first dielectric layer which extends along a sidewall of the first bonded substrate;
forming a conductive line which extends through the first dielectric layer and is connected to the first interconnect region;
forming a first electronic circuit which is carried by the first bonded substrate;
forming a second interconnect region which is carried by the first bonded substrate and connected to the first electronic circuit and the conductive line extending through the first dielectric layer.
10. The method of claim 9 , wherein the vertically oriented semiconductor device includes a mesa structure having a stack of semiconductor layers, and a control dielectric region extending annularly around the stack of semiconductor layers.
11. The method of claim 10 , wherein the control dielectric region includes an oxide layer and a nitride layer.
12. The method of claim 9 , wherein the vertically oriented semiconductor device operates as a memory device and the first semiconductor circuit controls the operation of the vertically oriented semiconductor device.
13. The method of claim 9 , wherein the first bonded semiconductor includes crystalline semiconductor material.
14. The method of claim 9 , further including providing a second bonded semiconductor substrate which is bonded to the second interconnect region through a second bonding interface.
15. The method of claim 14 , further including forming a second dielectric layer which extends along a sidewall of the second bonded substrate.
16. The method of claim 15 , further including forming a conductive line which extends through the second dielectric layer and is connected to the second interconnect region.
17. The method of claim 16 , further including forming a second electronic circuit which is carried by the second bonded substrate.
18. The method of claim 17 , further including forming a third interconnect region which is carried by the second bonded substrate and is connected to the second electronic circuit and the conductive line extending through the second dielectric layer.
19. The method of claim 9 , wherein the vertically oriented semiconductor device includes a dual gate.