Internal write/read pulse generating circuit of a semiconductor memory apparatus

1. An internal write/read pulse generating circuit of a semiconductor memory apparatus comprising:

a control clock generating unit configured to output a clock as a control clock when a column address strobe pulse is input and fix the control clock to a specific level when an all bank precharge signal or a refresh signal is enabled; and

an internal pulse generating unit configured to receive an external write pulse, an external read pulse, and the control clock, and generate an internal write pulse and an internal read pulse,

wherein the internal pulse generating unit generates the internal write pulse in response to the control clock after the external write pulse is input or generates an internal read pulse in response to the control clock after the external read pulse is input, and the external write pulse and the external read pulse are input from external of the internal write/read pulse generating circuit.

2. The internal write/read pulse generating circuit of a semiconductor memory apparatus of claim 1 , wherein the control clock generating unit includes:

an enable signal generating unit configured to enable an enable signal when the column address strobe pulse is input and disable the enable signal when a reset signal is enabled;

a controlling unit configured to output the clock as the control clock when the enable signal is enabled and fix the control clock to the specific level when the enable signal is disabled; and

a reset signal generating unit configured to enable the reset signal when the all bank precharge signal or the refresh signal is enabled.

3. The internal write/read pulse generating circuit of a semiconductor memory apparatus of claim 2 , wherein the enable signal generating unit includes flip flops.

4. The internal write/read pulse generating circuit of a semiconductor memory apparatus of claim 2 , wherein the reset signal generating unit is configured to disable the reset signal when both the all bank precharge signal and the refresh signal are disabled.

5. The internal write/read pulse generating circuit of a semiconductor memory apparatus of claim 4 , wherein the reset signal generating unit is configured to enable the reset signal when a power up signal is disabled and enable the reset signal in response to the all bank precharge signal and the refresh signal when the power up signal is enabled.

6. An internal write/read pulse generating circuit of a semiconductor memory apparatus configured to generate an internal write pulse after a predetermined number of clock periods of a clock when an external write pulse is input from external of the internal write/read pulse generating circuit or generate an internal read pulse when an external read pulse is input from external of the internal write/read pulse generating circuit,

wherein when a column address strobe pulse is input, transistors responding to the clock among transistors comprising the internal write/read pulse generating circuit repeat a turn on or turn off operation according to the clock and when an all bank precharge signal or a refresh signal is enabled, the transistors responding to the clock are fixed to either of the turn on or turn off state according to a fixed level of the clock.

7. The internal write/read pulse generating circuit of a semiconductor memory apparatus of claim 6 , wherein the internal write/read pulse generating circuit includes:

a control clock generating unit configured to output the clock as a control clock when the column address strobe pulse is input and fixes the control clock to a specific level when the all bank precharge signal or the read signal is enabled; and

an internal pulse generating unit configured to include the transistors repeating turn on or turn off in response to the control clock, the internal pulse generating uint configured to output the external write pulse as the internal write pulse or the external read pulse as the internal read pulse after a predetermined number of periods of the control clock when the external write pulse or the external read pulse is input.

8. The internal write/read pulse generating circuit of a semiconductor memory apparatus of claim 7 , wherein the control clock generating unit includes:

an enable signal generating unit configured to enable an enable signal when the column address strobe pulse is input and disable the enable signal when a reset signal is enabled;

a controlling unit configured to output the clock as the control clock when the enable signal is enabled and fix the control clock to the specific level when the enable signal is disabled; and

a reset signal generating unit configured to enable the reset signal when the all bank precharge signal or the refresh signal is enabled.

9. The internal write/read pulse generating circuit of a semiconductor memory apparatus of claim 8 , wherein the reset signal generating unit is configured to enable the reset signal when a power up signal is disabled and enable the reset signal in response to the all bank precharge signal and the refresh signal when the power up signal is enabled.