IP Library Granted Patent US 8,319,317
Granted Patent B2
US 8,319,317 · App. 12/481,292 · Granted Nov 27, 2012

Mesa type semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 8,319,317
App. No.
12/481,292
Granted
Nov 27, 2012
Kind
B2
Abstract

Problems with a conventional mesa type semiconductor device, which are deterioration in a withstand voltage and occurrence of a leakage current caused by reduced thickness of an insulation film on an inner wall of a mesa groove corresponding to a PN junction, are solved using an inexpensive material, and a mesa type semiconductor device of high withstand voltage and high reliability is offered together with its manufacturing method. A stable protection film made of a thermal oxide film is formed on the inner wall of the mesa groove in the mesa type semiconductor device to cover and protect the PN junction, and an insulation film having negative electric charges is formed to fill a space in the mesa groove covered with the thermal oxide film so that an electron accumulation layer is not easily formed at an interface between an N − type semiconductor layer and the thermal oxide film. With the structure described above, an influence of the positive electric charges in the thermal oxide film is weakened and an extension of a depletion layer into the N − type semiconductor layer at the interface with the thermal oxide film is secured.

Claims (39)

1. A mesa type semiconductor device comprising:

a semiconductor substrate of a first general conductivity type;

a first semiconductor layer of the first general conductivity type disposed on the semiconductor substrate, an impurity concentration of the first semiconductor layer being lower than an impurity concentration of the semiconductor substrate;

a second semiconductor layer of a second general conductivity type disposed on the first semiconductor layer so as to form a PN junction between the first and second semiconductor layers;

a mesa groove penetrating into the semiconductor substrate through the first and second semiconductor layers;

an oxide film disposed on the second semiconductor layer and in the mesa groove;

an organic insulation film disposed in the mesa groove so as to cover the oxide film at the PN junction and only a portion of the top surface of the second semiconductor layer, the portion being adjacent to and contiguous with the groove, the organic insulation film being in contact with the oxide film at the covered portion of the top surface of the second semiconductor layer; and

a wiring disposed on the oxide film.

2. The semiconductor device of claim 1 , wherein the organic insulation film comprises an organic resist or an epoxy resin.

3. The semiconductor device of claim 1 , further comprising a passivation film disposed on the organic insulation film so as to be in contact with the oxide film.

4. The semiconductor device of claim 3 , wherein a width of the passivation film is larger than a width of the mesa groove.

5. A mesa type semiconductor device comprising:

a semiconductor substrate of a first general conductivity type;

a first semiconductor layer of the first general conductivity type disposed on the semiconductor substrate, an impurity concentration of the first semiconductor layer being lower than an impurity concentration of the semiconductor substrate;

a second semiconductor layer of a second general conductivity type disposed on the first semiconductor layer so as to form a PN junction between the first and second semiconductor layers;

a mesa groove penetrating into the semiconductor substrate through the first and second semiconductor layers;

an oxide film disposed in the mesa groove so as to fill the mesa groove substantially completely and to cover only a portion of a top surface of the second semiconductor layer;

an organic insulation film disposed on the oxide film; and

a wiring disposed on the oxide film.

6. The semiconductor device of claim 5 , wherein the organic insulation film comprises an organic resist or an epoxy resin.

7. The mesa type semiconductor device of claim 5 , wherein a width of the mesa groove is 5 μm or smaller.

8. A method of manufacturing a mesa type semiconductor device, comprising:

providing a semiconductor substrate of a first general conductivity type;

forming a first semiconductor layer of the first general conductivity type on the semiconductor substrate, an impurity concentration of the first semiconductor layer being lower than an impurity concentration of the semiconductor substrate;

forming a second semiconductor layer of a second general conductivity type on the first semiconductor layer;

forming a mask on the second semiconductor layer;

etching the second semiconductor layer, the first semiconductor layer and the semiconductor substrate using the mask so as to form a groove so that the semiconductor substrate is exposed at a bottom of the groove;

forming an oxide film in the groove and on a top surface of the second semiconductor layer; and

forming an organic insulation film in the groove so as to cover the oxide film and only a portion of the top surface of the second semiconductor layer, the portion being adjacent to and contiguous with the groove, the organic insulation film being formed so as to have a dent at and above the groove.

9. The method of claim 1 , wherein the organic insulation film comprises an organic resist or an epoxy resin.

10. A method of manufacturing a mesa type semiconductor device, comprising:

providing a semiconductor substrate of a first general conductivity type;

forming a first semiconductor layer of the first general conductivity type on the semiconductor substrate, an impurity concentration of the first semiconductor layer being lower than an impurity concentration of the semiconductor substrate;

forming a second semiconductor layer of a second general conductivity type on the first semiconductor layer;

forming a mask on the second semiconductor layer;

etching the second semiconductor layer, the first semiconductor layer and the semiconductor substrate using the mask so as to form a groove so that the semiconductor substrate is exposed at a bottom of the groove; and

forming an oxide film so as to fill the groove substantially completely and to cover only a portion of a top surface of the second semiconductor layer.

11. The method of claim 10 , further comprising forming an organic insulation film on the oxide film.

12. The method of claim 11 , wherein the organic insulation film comprises an organic resist or an epoxy resin.

Assignments (14)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2016
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038994/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2016
From: ON SEMICONDUCTOR NIIGATA CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038988/0804 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CHANGE OF NAME Recorded Aug 11, 2015
From: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
To: ON SEMICONDUCTOR NIIGATA CO., LTD.
Reel/Frame 036327/0871 →
CHANGE OF NAME Recorded Aug 11, 2015
From: SANYO SEMICONDUCTOR CO., LTD.
To: SYSTEM SOLUTIONS CO., LTD
Reel/Frame 036300/0238 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER LISTED ON THE NAME CHANGE USP 7619299 PREVIOUSLY RECORDED ON REEL 025762, FRAME 0635 Recorded Jun 6, 2011
From: NIGATA SANYO ELECTRIC CO., LTD.
To: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 026424/0676 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 7619299, PREVIOUSLY RECORDED ON REEL 025762 FRAME 0320.ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT Recorded Jun 2, 2011
From: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
To: NIGATA SANYO ELECTRIC CO., LTD.
Reel/Frame 026654/0343 →
COMPANY SPLIT Recorded Dec 22, 2010
From: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
To: NIGATA SANYO ELECTRIC CO., LTD.
Reel/Frame 025762/0320 →
CHANGE OF NAME Recorded Dec 22, 2010
From: NIGATA SANYO ELECTRIC CO., LTD.
To: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 025762/0635 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2009
From: SEKI, KATSUYUKI; TSUCHIYA, NAOFUMI; SUZUKI, AKIRA; OKADA, KIKUO
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.; SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 022827/0974 →