Simultaneous and selective partitioning of via structures using plating resist
Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.
1. A multilayer printed circuit board, comprising:
at least one sub-composite structure having a plurality of layers including a dielectric layer arranged between a first conductive layer and a second conductive layer;
at least one clearance located in the plurality layers of the at least one sub-composite structure;
a plating resist selectively deposited in the at least one clearance;
a through-hole formed through the plurality of the at least one sub-composite structure and passing through the plating resist, an interior surface of the through-hole plated with a conductive material in areas of the interior surface that are devoid of the plating resist to form a partitioned via structure extending through two or more conductive layers in the plurality of layers of the at least one sub-composite structure, the partitioned via structure having a first segment electrically isolated from a second segment; and
a voltage switchable dielectric material at least partially filling the partitioned via structure and extending from the first segment to the second segment.
2. The printed circuit board of claim 1 , wherein the first segment is coupled to the first conductive layer in the at least one sub-composite structure and wherein the second segment is coupled to the second conductive layer in the at least one sub-composite structure.
3. The printed circuit board of claim 1 , wherein the voltage switchable dielectric material provides programmable circuit routing and a signal path from the first segment to the second segment in the multilayer printed circuit board.
4. The printed circuit board of claim 1 , wherein the first segment is coupled to a first signal trace and the second segment is coupled to a second signal trace and wherein the first segment is selectively and electrically coupled to the second segment through the voltage switchable dielectric material.
5. The printed circuit board of claim 1 , wherein the voltage switchable dielectric material provides transient signal protection to electrical components coupled to the first conductive layer or the second conductive layer.
6. The printed circuit board of claim 1 , wherein the first conductive layer is a power plane and the second conductive layer is a ground plane.
7. The printed circuit board of claim 1 , wherein the at least one sub-composite structure includes at least one power plane and at least one a ground plane.
8. The printed circuit board of claim 1 , wherein the first segment and second segment are separated along a diameter of the partitioned via structure.
9. The printed circuit board of claim 1 , further comprising:
a catalyzing material arranged between the interior surface of the through-hole and the conductive material.
10. The printed circuit board of claim 1 , wherein the at least one clearance has a radius greater than a radius of the partitioned via structure.
11. The printed circuit board of claim 1 , wherein the at least one clearance includes a top surface and a bottom surface and wherein the plating resist deposited in the at least one clearance is substantially level with the top surface of the at least one clearance.
12. The printed circuit board of claim 1 , wherein the at least one clearance includes a top surface and a bottom surface and wherein the plating resist extends beyond the top surface of the at least one clearance into at least one layer of the at least one sub-composite structure located above the top surface of the at least one clearance.
13. The printed circuit board of claim 1 , wherein the plating resist comprises an insulating hydrophobic resinous material resistant to a deposition of a catalytic species capable of catalyzing an electroless metal deposition.
14. The printed circuit board of claim 1 , wherein the plating resist is one of a dry film, a paste and a viscous liquid.
15. A sub-composite structure for use with a multilayer printed circuit board, comprising:
one or more layers including a dielectric layer arranged between a first conductive layer and a second conductive layer;
at least one clearance located in the one or more layers;
a plating resist selectively deposited in the at least one clearance;
a through-hole formed through the one or more layers and passing through the plating resist, an interior surface of the through-hole plated with a conductive material in areas of the interior surface that are devoid of the plating resist to form a partitioned via structure through the one or more layers, the partitioned via structure having a first segment electrically isolated from a second segment; and
a voltage switchable dielectric material at least partially filling the partitioned via structure and extending from the first segment to the second segment.
16. The printed circuit board of claim 15 , wherein the voltage switchable dielectric material forms a programmable circuit route and a signal path from the first segment to the second segment.
17. The printed circuit board of claim 15 , wherein the material is an ohmically resistive paste so that an integrated resistor is formed along the partitioned via structure.
18. The printed circuit board of claim 15 , wherein the first segment is coupled to the first conductive layer and wherein the second segment is coupled to the second conductive layer.
19. The printed circuit board of claim 15 , wherein the first conductive layer is a power plane and the second conductive layer is a ground plane.
20. The printed circuit board of claim 15 , further comprising: a catalyzing material arranged between the interior surface of the through-hole and the conductive material.
21. A multilayer printed circuit board, comprising:
at least one sub-composite structure having one or more layers including a dielectric layer arranged between a first conductive layer and a second conductive layer, where the first conductive layer is a power plane and the second conductive layer is a ground plane;
at least one clearance located in the one or more layers of the at least one sub-composite structure;
a plating resist selectively deposited in the at least one clearance;
a through-hole formed through the one or more layers of the at least one sub-composite structure and passing through the plating resist, an interior surface of the through-hole plated with a catalyzing material and further coated with a conductive material in areas of the interior surface that are devoid of the plating resist to form a partitioned via structure through the one or more layers of the at least one sub-composite structure, the partitioned via structure having a first segment electrically isolated from a second segment; and
a voltage switchable dielectric material at least partially filling the partitioned via structure and extending from the first segment to the second segment, where the first segment is coupled to a first signal trace and the second segment is coupled to a second signal trace and where the first segment is programmed to the second segment through the voltage switchable dielectric material;
wherein the voltage switchable dielectric material provides transient signal protection to electrical components connected to the first conductive layer or the second conductive layer and a programmable circuit routing and a signal path from the first segment to the second segment; and
wherein the at least one clearance has a radius greater than a radius of the partitioned via structure.