Receiver of semiconductor memory apparatus

1. A receiver of a semiconductor memory apparatus, comprising:

a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level;

a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level;

a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON;

a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON;

a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and

a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.

2. The receiver of claim 1 , wherein the first input transistor is an NMOS transistor which is coupled to the first output node voltage control unit and the second input transistor is a PMOS transistor which is coupled to the second output node voltage control unit.

3. The receiver of claim 2 , wherein the first output node voltage control unit increases the voltage level of the output node when the first input transistor is turned ON to decrease a voltage level of a node connected to the first output node voltage control unit, and

wherein the second output node voltage control unit decreases the voltage level of the output node when the second input transistor is turned ON to increase a voltage level of a node connected to the second output node voltage control unit.

4. The receiver of claim 1 , wherein the third input transistor is the PMOS transistor and the fourth input transistor is the NMOS transistor.

5. A receiver of a semiconductor memory apparatus, comprising:

a first input section, which is driven by a difference of a voltage level between a first node and a second node, configured to connect the first node to an output node when an input signal is at a high level and connect the second node to the output node when the input signal is at a low level; and

a second input section configured to connect the second node to the output node when an inversion signal of the input signal is at a high level and connect the first node to the output node when the inversion signal of the input signal is at a low level.

6. The receiver of claim 5 , wherein the first input section includes:

a first input transistor configured to be turned ON when the input signal is at a high level;

a second input transistor configured to be turned ON when the input signal is at a low level;

a first output node voltage control unit configured to couple the first node to the output node when the first input transistor is turned ON; and

a second output node voltage control unit configured to couple the second node to the output node when the second input transistor is turned ON.

7. The receiver of claim 6 , wherein the first input transistor is an NMOS transistor and the second input transistor is a PMOS transistor.

8. The receiver of claim 5 , wherein the second input section includes:

a first input transistor configured to couple the second node to the output node when the inversion signal is at a high level; and

a second input transistor configured to couple the first node to the output node when the inversion signal is at a low level.

9. The receiver of claim 8 , wherein the first input transistor comprises a NMOS transistor and the second input transistor comprises a PMOS transistor.