IP Library Granted Patent US 8,370,777
Granted Patent B2
US 8,370,777 · App. 12/485,238 · Granted Feb 5, 2013

Method of generating a leadframe IC package model, a leadframe modeler and an IC design system

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Quick Facts
Patent No.
US 8,370,777
App. No.
12/485,238
Granted
Feb 5, 2013
Kind
B2
Abstract

A method of generating a model of a leadframe IC package, a leadframe modeler and an IC design system are disclosed. In one embodiment the method includes: (1) adding connectivity information to a geometric representation of a leadframe, wherein the connectivity information represents electrical connections between the IC die and leads of the leadframe and (2) formatting the leads to represent BGA point of contacts for the IC die.

Claims (34)

1. A method of generating a model of a leadframe integrated circuit package having leads for electrically connecting an integrated circuit die to a substrate, comprising:

adding connectivity information to a geometric representation of a leadframe to provide a leadframe model, said adding includes propagating a net-list through a wire-bond file of said integrated circuit die, a ball grid array (BGA) file associated with said integrated circuit die and said leadframe model, wherein said connectivity information represents electrical connections between said integrated circuit die and leads of said leadframe; and

formatting, by using a computer, said leads of said leadframe as ball grid array points of contact for said integrated circuit die, including formatting said leads as a BGA input file to simulate said leadframe with a simulator tool.

2. The method as recited in claim 1 further comprising converting said leadframe model from a two-dimensional model to a three-dimensional model.

3. The method as recited in claim 1 wherein said geometric representation is based on a two-dimensional leadframe drawing from a computer aided design tool.

4. The method as recited in claim 1 wherein said connectivity information includes data selected from the group consisting of:

integrated circuit die data,

net-list data,

lead data, and

component data.

5. The method as recited in claim 1 wherein said adding said connectivity information includes defining a relationship of a mold cap of said integrated circuit die to lead extensions of said geometric representation.

6. The method as recited in claim 1 wherein said adding said connectivity information includes assigning bond finger numbers for each of said leads.

7. The method as recited in claim 1 wherein said adding said connectivity information includes adding cross-section information of said leads to said leadframe model.

8. A non-transitory computer readable medium embodying a leadframe modeler as a series of operating instructions configured to direct the operation of a processor, when executed, to perform steps, comprising:

storing a geometric representation of a leadframe for electrically connecting an integrated circuit die to a substrate; and

providing a leadframe model by adding connectivity information to said geometric representation for electrical connections between said integrated circuit die and leads of said leadframe and formatting said leadframe model as a ball grid array (BGA) input file to simulate the leadframe with a simulator tool, wherein said adding connectivity information includes propagating a net-list through a wire-bond file of said integrated circuit die, a BGA file associated with said integrated circuit die and said leadframe model, said leadframe model representing said leads as ball grid array contact points.

9. The non-transitory computer readable medium as recited in claim 8 further comprising converting said leadframe model from a two-dimensional model to a three-dimensional model.

10. The non-transitory computer readable medium as recited in claim 8 wherein said geometric representation is based on a leadframe drawing from a computer aided design tool.

11. The non-transitory computer readable medium as recited in claim 8 wherein said connectivity information includes data selected from the group consisting of:

integrated circuit die data,

net-list data,

lead data, and

component data.

12. The non-transitory computer readable medium as recited in claim 8 wherein said adding connectivity information includes defining a relationship of a mold cap of said integrated circuit die to lead extensions of said geometric representation.

13. The non-transitory computer readable medium as recited in claim 8 wherein said adding connectivity information includes assigning bond finger numbers for each of said leads.

14. The non-transitory computer readable medium as recited in claim 8 wherein said adding connectivity information includes information by adding cross-section information of said leads to said leadframe model.

15. An integrated circuit design system, comprising:

a processor;

a data storage coupled to the processor;

program code stored within the data storage and executable by the processor to cause the integrated circuit design system to perform:

adding connectivity information to a geometric representation of a leadframe to provide a leadframe model, said adding includes propagating a net-list through a wire-bond file of said integrated circuit die, a ball grid array (BGA) file associated with said integrated circuit die and said leadframe model, wherein said connectivity information represents electrical connections between said integrated circuit die and leads of said leadframe; and

formatting said leads to represent BGA points of contact for said integrated circuit die, including formatting said leads as a BGA input file to simulate said leadframe with a simulator; and

an extractor configured to convert said leadframe model from a two-dimensional model to a three-dimensional-dimensional leadframe model.

16. The integrated circuit design system of claim 15 further comprising an analyzer configured to analyze results generated by said simulator.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2009
From: HAWK, DONALD E., JR.; KING, STEPHEN M.; KLEMOVAGE, JEFFREY M.; KRANTZ, JOHN J.; LIM, ALLEN S.; REBELO, ASHLEY; SERGI, RICHARD J.
To: LSI CORPORATION
Reel/Frame 022830/0730 →