Memory using multiple supply voltages
View Patent ↗A memory has a method of operating that includes performing operations of a first type and a second type. A first voltage is coupled to a power supply node of a first memory cell of a memory array during a first operation of the first type. The first voltage is decoupled from the power supply node in response to terminating the first operation of the first type so as to allow the power supply node to drift. If the power supply node drifts to a second voltage, a power supply source is coupled to the power supply node. This is useful in reducing power in the circuit that produces the first voltage.
1. A method of operating a memory for performing operations of a first type and a second type, comprising:
coupling a first voltage at a first level to a power supply node of a first memory cell of a memory array during a first operation of the first type;
decoupling the first voltage from the power supply node in response to terminating the first operation of the first type so as to allow the power supply node to drift; and
in response to detecting that the power supply node drifts to a voltage at a second level, wherein a power supply terminal has a voltage at the second level, coupling the power supply node to the power supply terminal to maintain the power supply node at the second level.
2. The method of claim 1 , further comprising:
if a second operation of the first type is initiated before the power supply node drifts to the second level, coupling the first voltage to the power supply node.
3. The method of claim 1 , further comprising:
generating the first voltage by charge pumping.
4. The method of claim 3 , further comprising performing a first operation of the second type with the power supply node at the second level.
5. The method of claim 4 , wherein the first operation of the first type is a first read operation, further comprising:
if a second read operation is initiated before the power supply node drifts to the second level, coupling the first voltage to the power supply node.
6. The method of claim 3 , wherein the step of generating is further characterized by the charge pumping using the voltage at the power supply terminal to generate the first voltage so that the first level is greater than the second level.
7. The method of claim 1 , further comprising:
coupling a voltage at a third level greater than the second level and less than the first level to the power supply node in response to initiating a first operation of the second type.
8. The method of claim 1 , wherein the memory comprises an integrated circuit and the voltage at the power supply terminal is supplied external to the integrated circuit.
9. The method of claim 1 , wherein the first type is a read, the second type is a write, and the first level is less than the second level.
10. The method of claim 1 , wherein, the step of coupling a power supply node to the power supply terminal results in a voltage at the power supply node such that data present in the first memory cell is retained and the power supply node is able to be charged to the first level so as to perform a read operation of the first memory cell.
11. The method of claim 1 wherein the memory has an array that is arranged in a plurality of columns of memory cells, wherein all memory cells of a first column of the plurality of columns, including the first memory cell, are coupled to the power supply node.
12. The method of claim 1 wherein the memory has an array that is arranged in a plurality of rows of memory cells, wherein all memory cells of a first row of the plurality of rows, including the first memory cell, are coupled to the power supply node.
13. The method of claim 1 wherein the memory has an array of memory cells including the first memory cell, wherein all memory cells of the array are coupled to the power supply node.
14. A memory formed on an integrated circuit, comprising:
a memory array having a plurality of memory cells including a first memory cell having a power supply node;
a first power supply generator, coupled to a power supply terminal, having an output terminal providing a voltage at a first level;
a first switching device that couples the power supply node to the output terminal during a first operation of a first type and decoupling the power supply node from the output terminal in response to a termination of the first operation of the first type; and
a second switching device that couples the power supply node to the power supply terminal in response to detecting that the power supply node has drifted to a voltage at a second level, wherein a voltage present at the power supply terminal has the second level.
15. The memory of claim 14 , wherein the first switching device comprises a first transistor having a control electrode for receiving a read signal, a first current electrode coupled to the power supply node, and a second current electrode coupled to the output terminal.
16. The memory of claim 15 , wherein the second switching device comprises a second transistor having a gate for receiving a power enable signal, a first current electrode coupled to the power supply terminal, and a second current electrode coupled to the power supply node.
17. The memory of claim 16 , further comprising a comparator having a first input coupled to the power supply terminal, a second input coupled to the power supply node, and an output coupled to the gate of the second switching device.
18. The memory of claim 17 , wherein the first type is a read.
19. A method of operating a memory, comprising:
coupling a read voltage to a power supply node of a first memory cell of a memory array during a first read operation, wherein the read voltage is at a first level;
decoupling the read voltage from the power supply node in response to terminating the first read operation to allow the power supply node to drift downward;
coupling a power supply source having a voltage at a second level to the power supply node in response to power supply node drifting to the second level; and
in response to initiating a second read operation, coupling the read voltage to the power supply node.
20. The memory of claim 19 , further comprising:
in response to initiating a write operation, coupling a write voltage having one of a group consisting of the second level and a third level, wherein the third level is different than the second level and less than the first level.