Method of fabricating semiconductor integrated circuit device
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
1. A method of fabricating a semiconductor integrated circuit device, comprising:
(a) forming a gate electrode over a silicon surface of a wafer, the gate electrode having a silicon film to be a poly-silicon conductive film;
(b) forming a source region and a drain region over the silicon surface of the wafer;
(c) depositing a Co film on the source region, the drain region and the gate electrode, by sputtering, from a Co sputtering target which, apart from carbon and oxygen impurities, is at least 99.99 wt. % pure, and wherein a sum of Fe and Ni in the Co sputtering target is not greater than 50 ppm by weight;
(d) performing a first rapid thermal annealing at a first temperature to a surface covered with the Co film so as to form Co monosilicide film;
(e) removing a remaining Co film not formed into Co monosilicide in the step (d); and
(f) after step (e), performing a second rapid thermal annealing at a second temperature higher than the first temperature to a surface covered with the Co monosilicide film so as to form Co disilicide film.
2. A method of fabricating a semiconductor integrated circuit device according to claim 1 , wherein the first temperature is not higher than 525° C.
3. A method of fabricating a semiconductor integrated circuit device according to claim 2 , wherein the semiconductor integrated circuit device is designed under design rules not larger than 0.25 micro-meter.
4. A method of fabricating a semiconductor integrated circuit device according to claim 3 , wherein the Co sputtering target includes a sum of Fe and Ni which is not greater than 10 ppm by weight.
5. A method of fabricating a semiconductor integrated circuit device according to claim 3 , wherein said Co sputtering target, apart from carbon and oxygen impurities, is 99.999 wt. % pure.
6. A method of fabricating a semiconductor integrated circuit device according to claim 3 , wherein said Co film is deposited with a thickness of 18-60 nm.
7. A method of fabricating a semiconductor integrated circuit device according to claim 3 , wherein the second temperature is from 650° C. to 800° C.
8. A method of fabricating a semiconductor integrated circuit device according to claim 7 , wherein the first temperature is not lower than 475° C.
9. A method of fabricating a semiconductor integrated circuit device according to claim 8 , wherein the Co sputtering target includes a sum of Fe and Ni which is not greater than 10 ppm by weight.
10. A method of fabricating a semiconductor integrated circuit device according to claim 8 , wherein said Co sputtering target, apart from carbon and oxygen impurities, is 99.999 wt. % pure.
11. A method of fabricating a semiconductor integrated circuit device according to claim 7 , wherein the Co sputtering target includes a sum of Fe and Ni which is not greater than 10 ppm by weight.
12. A method of fabricating a semiconductor integrated circuit device according to claim 7 , wherein said Co sputtering target, apart from carbon and oxygen impurities, is 99.999 wt. % pure.
13. A method of fabricating a semiconductor integrated circuit device according to claim 3 , wherein the first temperature is not lower than 475° C.
14. A method of fabricating a semiconductor integrated circuit device according to claim 3 , wherein each junction depth of the source region and the drain region is between 0.2 and 0.1 micro-meter.