Nonvolatile memory cell, nonvolatile memory device and method for driving the same
View Patent ↗A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other.
1. A nonvolatile memory cell, comprising:
a phase-change layer; and
a first gate and a second gate that are formed on sides of the phase-change layer to face each other across the phase-change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other gate, wherein the first and second gates are each in direct contact with the phase-change layer.
2. The nonvolatile memory cell of claim 1 , wherein the first gate is formed on one side of the phase-change layer and changes a crystalline state of a first surrounding region of the phase-change layer using heat generated by a current supplied thereto so that the first surrounding region has a high or low resistance characteristic, wherein the first gate is formed on the first surrounding region of the phase-change layer.
3. The nonvolatile memory cell of claim 2 , wherein the second gate is formed on the other side of the phase-change layer and changes a crystalline state of a second surrounding region of the phase-change layer using heat generated by a current supplied thereto so that the second surrounding region has a high or low resistance characteristic, wherein the second gate is formed on the second surrounding region of the phase-change layer.
4. A method for driving a nonvolatile memory cell, the method comprising:
a data writing step of writing data by supplying a reset current or a set current to a first gate;
a pre-readout step of supplying the reset current to a second gate; and
a readout step of reading out the data by detecting a state of a readout current supplied to a phase-change layer, wherein the nonvolatile memory cell includes the phase-change layer and includes the first and second gates formed on sides of the phase-change layer to face each other across the phase-change layer and to control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other gate and wherein the first and second gates are each in direct contact with the phase-change layer.
5. The method of claim 4 , after the readout step, further comprising a post-readout step of supplying the set current to the second gate.
6. The method of claim 5 , wherein, in the post-readout step, a surrounding region of the phase-change layer that is formed on the second gate is changed from a polycrystalline state to an amorphous state.
7. The method of claim 5 , wherein, in the data writing step, the pre-readout step and the post-readout step, a ground voltage is supplied to the phase-change layer.
8. The method of claim 4 , wherein, in the data writing step, data having a logic value ‘1’ is written in case where the reset current is supplied.
9. The method of claim 4 , wherein, in the data writing step, data having a logic value ‘0’ is written in case where the set current is supplied.
10. The method of claim 4 , wherein, in the data writing step, a surrounding region of the phase-change layer that is formed on the first gate is changed from a polycrystalline state to an amorphous state in case where the reset current is supplied.
11. The method of claim 4 , wherein, in the data writing step, a surrounding region of the phase-change layer that is formed on the first gate is changed to a polycrystalline state in case where the set current is supplied.
12. The method of claim 4 , wherein, in the pre-readout step, a surrounding region of the phase-change layer that is formed on the second gate is changed from a polycrystalline state to an amorphous state in case where the reset current is supplied.