Method for fabricating semiconductor device with vertical gate
View Patent ↗A method for fabricating a semiconductor device includes forming buried bit lines in a first substrate; forming a trench that separate the buried bit lines from each other; forming an interlayer insulation layer to gap-fill the trench; forming a second substrate over the first substrate gap-filled with the interlayer insulation layer; forming a protective pattern over the second substrate; forming a plurality of active pillars by etching the second substrate using the protective pattern as an etch barrier; and forming vertical gates surrounding sidewalls of the active pillars.
1. A method for fabricating a semiconductor device, comprising:
forming buried bit lines separated from each other by a respective trench in a substrate before a plurality of active pillars are formed;
forming the plurality of active pillars over the buried bit lines; and
forming vertical gates surrounding sidewalls of the active pillars.
2. The method of claim 1 , wherein the forming of the plurality of active pillars includes:
forming an active pillar substrate over the substrate including the buried bit lines;
forming a protective layer over the active pillar substrate;
etching the protective layer by using a first mask for forming the trench;
etching the protective layer by using a second mask that crosses the first mask to thereby form a protective pattern; and
etching the active pillar substrate by using the protective pattern as an etch barrier.
3. The method of claim 2 , wherein the first mask and the second mask are photoresist patterns formed of lines with spacing in-between.
4. The method of claim 2 , wherein the protective pattern includes a nitride layer or an oxide layer.
5. The method of claim 1 , wherein the active pillar substrate is formed by using an epitaxial growth method.
6. The method of claim 2 , wherein the active pillar substrate includes an epitaxial silicon layer.
7. The method of claim 1 , wherein the substrate includes a silicon layer.
8. The method of claim 1 , wherein the buried bit lines is formed by performing an impurity ion implantation.
9. A method for fabricating a semiconductor device, comprising:
forming buried bit lines in a first substrate before a plurality of active pillars are formed;
forming a trench that separate the buried bit lines from each other;
forming an interlayer insulation layer to gap-fill the trench;
forming a second substrate over the first substrate gap-filled with the interlayer insulation layer;
forming a protective pattern over the second substrate;
forming the plurality of active pillars by etching the second substrate using the protective pattern as an etch barrier; and
forming vertical gates surrounding sidewalls of the active pillars.
10. The method of claim 9 , wherein the forming of the protective pattern includes:
forming a protective layer over the second substrate;
etching the protective layer by using a first mask for forming the trench; and
etching the protective layer by using a second mask that crosses the first mask to thereby form the protective pattern.
11. The method of claim 10 , wherein the first mask and the second mask are photoresist patterns that form lines with spacing in-between.
12. The method of claim 10 , wherein the protective pattern includes a nitride layer or an oxide layer.
13. The method of claim 9 , wherein the second substrate is formed by using an epitaxial growth method.
14. The method of claim 9 , wherein the second substrate includes an epitaxial silicon layer.
15. The method of claim 9 , wherein the first substrate includes a silicon layer.
16. The method of claim 9 , wherein the buried bit lines are formed by performing an impurity ion implantation.