Layout of semiconductor device
View Patent ↗A layout of a semiconductor device is disclosed, which forms one transistor in one active region to reduce the number of occurrences of a bridge encountered between neighboring layers, thereby improving characteristics of the semiconductor device. Specifically, the landing plug connected to the bit line contact is reduced in size, so that a process margin of word lines is increased to increase a channel length, thereby reducing the number of occurrences of a bridge encountered between the landing plug and the word line.
1. A semiconductor device layout comprising: a first and a second “L” shaped active regions formed in a first row; a third and a fourth “L” shaped active regions formed in a second row;
a first word line passing between the first and the second “%” shaped active regions and extending across the third “L” shaped active region; and
a second word line extending across the second “L” shaped active region and passing between the third and the fourth “L” shaped active regions,
wherein the first, the second, the third, and the fourth “L” shaped active regions each have short regions and long regions,
wherein the short regions of the second and the third “L” shaped active regions are arranged in a same line along a first direction,
wherein the long regions of the first and the second “L” shaped active regions protrude along a second direction perpendicular to the first direction,
wherein the long region of the third and the fourth “L” shaped active region protrudes along a third direction opposite to the second direction,
wherein the first word line includes a first extension that overlaps with the short region of the third “L” shaped active region, and
wherein the second word line includes a second extension that overlaps with the short region of the second “L” shaped active region.
2. The semiconductor device layout according to claim 1 , wherein the short regions of the second and the third “L” shaped active regions are provided between the first word line and the second word line.
3. The semiconductor device layout according to claim 1 ,
wherein the second word line traverses over the long region of the second “L” shaped active region, and
wherein the first word line traverses over the long region of the third active region.
4. The semiconductor device layout according to claim 1 , wherein the first word line exposes first and second ends of the third “L” shaped active region, wherein the first end of the third “L” shaped active region extends in the third direction, wherein the second end of the third “L” shaped active region extends in the first direction,
wherein the second word line exposes first and second ends of the second “L” shaped active region, wherein the first end of the second “L” shaped active region extends in the second direction, wherein the second end of the second “L” shaped active region extends in the first direction, and
wherein the device layout further comprises:
a first bit line landing plug formed over the second end of the second “L” shaped active region that is exposed by the second word line:
a second bit line landing plug formed over the second end of the third “L” shaped active region that is exposed by the first word line;
a first storage electrode landing plug formed over the first end of the second “L” shaped active regions that is exposed by the second word line; and
a second storage electrode landing plug formed over the first end of the third “L” shaped active regions that is exposed by the first word line.
5. The semiconductor device layout according to claim 4 ,
wherein the first and the second bit line landing plugs are formed over the short regions of the second and the third “L” shaped active regions, respectively, and
wherein the first and the second storage electrode landing plugs are formed over the long regions of the second and the third “L” shaped active regions, respectively.
6. The semiconductor device layout according to claim 4 , the semiconductor device layout further comprising:
first and second bit line contacts formed over and coupled to the first and the second bit line landing plugs, respectively.
7. The semiconductor device layout according to claim 6 , the semiconductor device layout further comprising:
a bit line arranged perpendicular to the first and the second word lines,
wherein widths of the first and the second bit line contacts are no larger than widths of the first and the second bit line landing plugs, respectively.
8. The semiconductor device layout according to claim 4 , the semiconductor device layout further comprising:
first and second storage electrode contacts formed over and coupled to the first and the second storage electrode landing plugs, respectively.
9. The semiconductor device layout according to claim 4 , wherein the device layout further comprises:
a first storage electrode contact extending along the third direction and coupled to the first storage electrode landing plug; and
a second storage electrode contact extending along the second direction and coupled to the second storage electrode landing plugs.
10. The semiconductor device layout according to claim 9 , wherein the first and the second storage electrode contacts are each in square or rectangular shapes.
11. The semiconductor device layout according to claim 9 , the semiconductor device layout further comprising:
a first storage electrode formed over and coupled to the first storage electrode contact: and
a second storage electrode formed over and coupled to the second storage electrode contact,
wherein the first and the second storage electrodes are formed in zigzag format.
12. A semiconductor device layout comprising: first and second active regions in an “L” shape formed in an odd row; third and fourth active regions in an “L” shape formed in an even row;
a first word line passing between the first and the second active regions and traversing over the third active region;
a second word line traversing over the second active region and passing between the third and the fourth active regions;
a bit line landing plug formed over any of the second and the third active regions that are exposed by the first and second word lines respectively; and
a storage electrode landing plug formed over any of the second and the third active regions that are exposed by the first and second word lines respectively,
wherein the first, the second, the third, and the fourth active regions each have short regions and long regions,
wherein the long regions of the first and the second active regions protrude along a first direction,
wherein the long regions of the third and the fourth active regions protrude along a second direction opposite to the first direction, and
wherein the short regions of the second and the third active regions are arranged in a same line along a third direction perpendicular to the first direction.
13. The device of claim 12 , wherein the bit line landing plug is formed over the short region of any of the second and the third active regions, and the storage electrode landing plug is formed over the long region of any of the second and the third active regions.
14. The semiconductor device layout according to claim 1 ,
wherein the first and the second word lines are disposed adjacent to each other.
15. The semiconductor device layout according to claim 1 ,
wherein the short regions of the second and the third “L” shaped active regions are arranged along the first direction.