Semiconductor device and interface board for testing the same
View Patent ↗A semiconductor device includes a common probing pad; an internal voltage generation unit having a plurality of internal voltage generation blocks configured to generate a plurality of internal voltages; and a probing voltage selection unit configured to transfer an internal voltage selected from the internal voltages to the common probing pad in response to a plurality of voltage selection signals.
1. A semiconductor device, comprising:
a common probing pad;
an internal voltage generation unit having a plurality of internal voltage generation blocks configured to generate a plurality of internal voltages;
a probing voltage selection unit configured to transfer an internal voltage selected from the internal voltages to the common probing pad in response to a plurality of voltage selection signals;
a plurality of power pads configured to receive a plurality of test voltages provided from a test device; and
a forcing-voltage selection unit configured to perform forcing of the test voltages, which are applied to the power pads, to the internal voltage generation blocks in response to the voltage selection signals.
2. The semiconductor device of claim 1 , further comprising:
a test control unit configured to generate the voltage selection signals, wherein a same one of the voltage selection signals is configured to be used to control a selective application of one of test voltages provided from a test device to one of the plurality of internal voltage generation blocks and to control a transfer of the internal voltage of the internal voltage generation block to the common probing pad.
3. The semiconductor device of claim 1 , wherein the internal voltage generation blocks, respectively, include reference voltage generators configured to generate internal reference voltages and internal voltage generators configured to generate internal voltages corresponding to voltage levels of the internal reference voltages.
4. The semiconductor device of claim 3 , wherein the internal voltages are the internal reference voltages generated from the reference voltage generators.
5. The semiconductor device of claim 3 , wherein the internal voltages are the internal voltages generated from the internal voltage generators.
6. The semiconductor device of claim 1 , further comprising:
a test control unit configured to generate the voltage selection signals.
7. The semiconductor device of claim 1 , wherein the internal voltage generation blocks, respectively, include reference voltage generators configured to generate internal reference voltages and internal voltage generators configured to generate internal voltages corresponding to voltage levels of the internal reference voltage.
8. The semiconductor device of claim 7 , wherein the forcing-voltage selection unit is configured to perform forcing the test voltages to the reference voltage generators.
9. The semiconductor device of claim 7 , wherein the forcing-voltage selection unit is configured to perform forcing the test voltages to the internal voltage generators.
10. The semiconductor device of claim 1 , wherein the test voltages are commonly provided to the semiconductor devices through a common voltage channel of the test device.
11. The semiconductor device of claim 1 , wherein the probing voltage selection unit includes a plurality of switches configured to output an internal voltage selected from the internal voltages in response to the voltage selection signal.
12. The semiconductor device of claim 11 , wherein the switches are transmission gates.
13. The semiconductor device of claim 1 , wherein the forcing-voltage selection unit includes a plurality of switches configured to selectively output the test voltages in response to the voltage selection signal.
14. The semiconductor device of claim 13 , wherein the switches are transmission gates.
15. A test interface board, comprising:
a plurality of common voltage input terminals configured to receive a plurality of test voltages provided through a common voltage channel of a test device;
a plurality of test voltage transferring line group configured to be allocated to a plurality of semiconductor devices, respectively, and to each transfer the test voltages, which are applied to the common voltage input terminals, to the respective semiconductor device; and
a plurality of voltage transferring pins configured to couple the test voltage transferring line groups to a plurality of power pads of each of the semiconductor devices,
wherein the plurality test voltages are applied to a plurality of internal voltage generation blocks of each of the semiconductor devices,
wherein each of the semiconductor devices includes a common probing pad configured to selectively output one of the internal voltages generated from the internal voltage generation blocks.
16. The test interface board of claim 15 , wherein the common voltage channel has a plurality of voltage transferring interfaces configured to transfer the test voltages.
17. The test interface board of claim 15 , wherein each of the test voltage transferring line groups has a plurality of transfer lines configured to transfer the test voltages.