Semiconductor device and method of fabricating the same
View Patent ↗Provided are a semiconductor device and a method of fabricating the semiconductor memory device. A contact plug is formed by wet etching. An aspect ratio of SAC is decreased and SAC fail is reduced so that a process margin is secured. The semiconductor device includes a semiconductor substrate comprising an active region and a device isolation layer defining the active region, a conductive pattern formed on the semiconductor substrate, and a nitride layer formed on the semiconductor substrate perpendicularly to the conductive pattern.
1. A method of fabricating a semiconductor device, the method comprising:
providing a underlying layer including active regions and device isolation layers, each active region having first and second conductive regions;
forming conductive line patterns over the underlying layer, each conductive line pattern passing between the first and the second conductive regions;
forming an interlayer insulating layer over the underlying layer so as to fill between the conductive line patterns;
etching the interlayer insulating layer to form a trench extending across the conductive line patterns and passing over the device isolation layer between the active regions;
forming an insulating pattern within the trench, the insulating pattern being different material from the interlayer insulating layer;
wet etching the interlayer insulating layer using the insulating pattern and the conductive line pattern as an etch mask to form a contact hole for any of the first and the second conductive regions; and
forming a contact plug within the contact hole to electrically couple the contact plug and any of the first and the second conductive regions.
2. The method of claim 1 , wherein the insulating pattern and the interlayer insulating layer have different etch characteristics.
3. The method of claim 2 , wherein the insulating pattern includes nitride, and the interlayer insulating layer includes oxide.
4. The method of claim 1 , wherein the underlying layer is semiconductor material and the first and the second conductive regions are a source region and a drain region, respectively.
5. The method of claim 1 , wherein the conductive line pattern is a word line or a bit line.
6. The method of claim 1 , wherein the conductive line pattern exposes the first and the second conductive regions, and
wherein the method further comprising the step of forming an etch stop layer over the first and the second conductive line patterns.
7. The method of claim 6 , wherein the interlayer insulating layer is formed over the etch stop layer, and
wherein the wet etch is performed to remove the interlayer insulating layer at least until the etch stop layer is exposed.
8. The method of claim 7 , further comprising:
etching the exposed etch stop layer to expose the first and the second conduction regions, so that the contact plug formed within the contact hole contacts any of the first and the second conductive regions of the underlying layer.
9. The method of claim 8 , wherein the etch stop layer is etched using a gas including one or more of CF4, CHF3, O2, Ar, and N2.
10. The method of claim 1 , further comprising:
forming a contact spacer on a sidewall of the insulating pattern and a sidewall of any of the first and the second conductive line patterns.
11. The method of claim 1 , wherein, the interlayer insulating layer is etched to form the trench by using an etch gas including CF4, CHF3, O2, Ar, N2, C4F8, C4F6, and CH2F2.
12. The method of claim 1 , wherein the wet etching is performed using a buffered oxide etchant (BOE).