IP Library Granted Patent US 8,234,613
Granted Patent B2
US 8,234,613 · App. 12/497,022 · Granted Jul 31, 2012

Program, design apparatus, and design method for dynamic reconfigurable circuit

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Quick Facts
Patent No.
US 8,234,613
App. No.
12/497,022
Granted
Jul 31, 2012
Kind
B2
Abstract

A computer-readable recording medium that stores therein a computer program for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, the computer program enabling a computer to execute: acquiring a plurality of contexts having connection information between operation devices and network modules, wherein the operation devices and network modules are disposed in clusters, and connection information among the network modules; calculating a cluster count of the clusters and an operation device count for each operation device type of the operation devices in each cluster based on the acquired plurality of contexts; generating a circuit configuration for each context in which disposition of the operation devices in each cluster and connection of the network modules are made to satisfy the calculated cluster count and operation device count; and outputting the generated circuit configuration.

Claims (55)

1. A non-transitory computer-readable recording medium that stores therein a computer program for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, the computer program enabling a computer to execute:

acquiring a plurality of contexts having connection information between operation devices and network modules, wherein the operation devices and network modules are disposed in clusters, and connection information among the network modules;

calculating, by the computer, a cluster count of the clusters and an operation device count for each operation device type of the operation devices in each cluster based on the acquired plurality of contexts, the calculating being executed for every execution cycle;

generating a circuit configuration for each context in which disposition of the operation devices in each cluster and connection of the network modules are made to satisfy the calculated cluster count and operation device count; and

outputting the generated circuit configuration.

2. The non-transitory computer-readable recording medium according to claim 1 , wherein the calculating further comprises:

calculating the minimum required number of the operation devices as the operation device count.

3. The non-transitory computer-readable recording medium according to claim 1 , wherein the calculating further comprises:

calculating the minimum required number of the clusters as the cluster count.

4. The non-transitory computer-readable recording medium according to claim 1 , wherein the generating further comprises:

generating a circuit configuration that comprehensively includes the circuit configurations generated for the respective contexts, and

wherein outputting further comprises:

outputting at least any one of the circuit configurations generated for the respective contexts and the circuit configuration that comprehensively includes the respective circuit configurations.

5. The non-transitory computer-readable recording medium according to claim 1 , wherein generating further comprises:

generating a circuit configuration that satisfies constraint information on the dynamic reconfigurable circuit.

6. The non-transitory computer-readable recording medium according to claim 5 , wherein the computer program further enables the computer to execute:

determining for each circuit configuration whether or not the circuit configuration is a feasible configuration based on the constraint information on the dynamic reconfigurable circuit,

wherein generating further comprises:

generating a next-state circuit configuration in which the disposition of the operation devices or the connection of the network modules in the circuit configuration determined as not a feasible configuration has been modified to satisfy the cluster count and the operation device count.

7. The non-transitory computer-readable recording medium according to claim 1 , wherein the computer program further enables the computer to execute:

determining feasibility of the circuit configuration is a feasible configuration based on the cluster count and the operation device count,

wherein generating further comprises:

generating a next-state circuit configuration in which the disposition of the operation devices or the connection of the network modules in the circuit configuration determined as not a feasible configuration has been modified to satisfy the cluster count and the operation device count.

8. The non-transitory computer-readable recording medium according to claim 7 , wherein the computer program further enables the computer to execute:

determining adoption of the next-state circuit configuration by using an annealing method,

wherein outputting further comprises:

outputting the determined next-state circuit configuration.

9. The non-transitory computer-readable recording medium according to claim 8 , wherein determining feasibility further comprises:

determining feasibility of the determined next-state circuit configuration, and

wherein generating further comprises:

taking the next-state circuit configuration as a current-state circuit configuration if it is determined that the next-state circuit configuration is not a feasible configuration, and

generating a next-state circuit configuration in which the disposition of the operation devices or the connection of the network modules in the current-state circuit configuration has been modified to satisfy the cluster count and the operation device count.

10. The non-transitory computer-readable recording medium according to claim 7 , wherein outputting further comprises:

outputting the circuit configuration determined as feasible.

11. The non-transitory computer-readable recording medium according to claim 7 , wherein acquiring further comprises:

acquiring a general element configuration file in which the cluster count of the clusters and the operation device count for each operation device type in each cluster are preset, and

wherein generating further comprises:

adding an operation device to the circuit configuration based on a difference between the cluster count and the operation device count in the general element configuration file and the calculated cluster count and operation device count.

12. The non-transitory computer-readable recording medium according to claim 11 , wherein the computer program further enables the computer to execute:

determining, based on the difference, a type of the operation device to be added,

wherein generating further comprises:

adding the operation device of the operation device type to the circuit configuration.

13. The non-transitory computer-readable recording medium according to claim 12 , wherein the computer program further enables the computer to execute:

determining based on a connection state in the circuit configuration whether or not the operation device of the determined operation device type can be added, wherein

the generating further comprises adding the operation device of the determined operation device type to the circuit configuration if it is determined that the operation device can be added.

14. A design apparatus for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, comprising:

an acquisition unit for acquiring a plurality of contexts having connection information between operation devices and network modules, wherein the operation devices and network modules are disposed in clusters, and connection information among the network modules;

a calculation unit for calculating, for every execution cycle, a cluster count of the clusters and an operation device count for each operation device type of the operation devices in each cluster based on the plurality of contexts acquired by the acquisition unit;

a generation unit for generating a circuit configuration for each context in which disposition of the operation devices in each cluster and connection of the network modules are made to satisfy the cluster count and the operation device count calculated by the calculation unit; and

an output unit for outputting the circuit configuration generated by the generation unit.

15. A method for designing a dynamic reconfigurable circuit in which a plurality of circuit configurations are implemented with a single circuit, the method enabling a computer to execute:

acquiring a plurality of contexts having connection information between operation devices and network modules, wherein the operation devices and network modules are disposed in clusters, and connection information among the network modules;

calculating, by the computer, a cluster count of the clusters and an operation device count for each operation device type of the operation devices in each cluster based on the acquired plurality of contexts, the calculating being executed for every execution cycle;

generating a circuit configuration for each context in which disposition of the operation devices in each cluster and connection of the network modules are made to satisfy the cluster count and the operation device count calculated by the calculating; and

outputting the generated circuit configuration.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 22, 2017
From: MORGAN STANLEY SENIOR FUNDING, INC
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 044949/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 21, 2017
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 044938/0360 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0256 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024748/0328 →
ASSIGNMENT OF ASSIGNOR'S RIGHT, TITLE AND INTEREST Recorded Mar 5, 2010
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 024035/0224 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2009
From: TABARU, TSUGUCHIKA; OHZEKI, RYUICHI; NOMIMURA, KATSUMOTO; SUZUKI, TOSHIHIRO; KATOU, KIYOMITSU
To: FUJITSU LIMITED
Reel/Frame 022930/0758 →