Edge seal for a semiconductor device
View Patent ↗In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.
1. An edge seal region of a semiconductor die comprising:
a substrate of a first conductivity type having a surface;
a semiconductor die formed on the substrate, the semiconductor die having an interior section wherein active devices are formed and also having an exterior edge that is distal from the interior section;
a field oxide layer on the surface of the substrate and extending toward the exterior edge of the semiconductor die, the field oxide layer having an exterior edge;
an inter-layer dielectric on the field oxide layer and having an exterior edge that is substantially co-terminus with the exterior edge of the field oxide layer;
a doped region of the first conductivity type on the surface of the semiconductor substrate and substantially self-aligned with the exterior edge of the inter-layer dielectric; and
a metal layer mechanically contacting the doped region and the exterior edge of the field oxide layer.
2. The edge seal region of claim 1 further including a portion of the surface of the substrate extending from the metal layer to the exterior edge of the semiconductor die wherein the metal layer does not overlie the portion of the surface of the substrate.
3. The edge seal region of claim 1 further including a portion of the surface of the substrate extending from the metal layer to the exterior edge of the semiconductor die wherein the inter-layer dielectric does not overlie the portion of the surface of the substrate.
4. The edge seal region of claim 1 further including a portion of the surface of the substrate extending from the metal layer to the exterior edge of the semiconductor die wherein the field oxide layer does not overlie the portion of the surface of the substrate.
5. The edge seal region of claim 1 further including another metal layer on the inter-layer dielectric wherein the another metal layer electrically and mechanically contacts the metal layer.
6. The edge seal region of claim 5 further including another inter-layer dielectric on the another metal layer.
7. The edge seal region of claim 1 further including another inter-layer dielectric on the inter-layer dielectric.
8. The edge seal region of claim 1 further including a plurality of bonding pads positioned between the interior section of the semiconductor die and the edge seal region.
9. The edge seal region of claim 1 wherein the doped region is located between the semiconductor die and a second semiconductor die.