IP Library Granted Patent US 7,928,771
Granted Patent B2
US 7,928,771 · App. 12/499,879 · Granted Apr 19, 2011

Drive signal output circuit and multi-chip package

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Quick Facts
Patent No.
US 7,928,771
App. No.
12/499,879
Granted
Apr 19, 2011
Kind
B2
Abstract

Input signals from a signal input terminal are input to a logic circuit, and a control signal corresponding to states of the input signals is output. The control signal is supplied to an output circuit, a plurality of transistors are controlled, and a drive signal is output corresponding to states of the transistors. In the logic circuit, the logic is switched according to the polarity of the setting signal which is input to a logic setting terminal, and a control signal corresponding to the input signal is changed.

Claims (26)

1. A driving signal output circuit comprising:

a signal input terminal to which two input signals are input;

a logic circuit to which the two input signals from the signal input terminal are input and which outputs a plurality of control signals corresponding to four states created by high level and low level of the two input signals;

an output circuit which includes a plurality of transistors which are controlled by the plurality of control signals, and which outputs a drive signal for driving a load, the drive signal corresponding to states of the plurality of transistors; and

a logic setting terminal to which a setting signal is input, wherein the setting signal assumes either high level or low level, wherein

the plurality of control signals have:

a first mode for controlling the plurality of transistors of the output circuit to generate four states in accordance with the four states of the input signals, wherein the generated four states include a state in which a current is supplied to the load in a forward direction, a state in which a current is supplied to the load in a backward direction, a state in which the terminals of the load are isolated, and a state in which the terminals of the load are short-circuited; and

a second mode for controlling the plurality of transistors of the output circuit to generate three states in accordance with the four states of the input signals, wherein the generated three states include a state in which a current is supplied to the load in a forward direction, a state in which a current is supplied to the load in a backward direction, and a state in which the terminals of the load are isolated, and

in the logic circuit, whether to generate the plurality of control signals of the first mode or to generate the plurality of control signals of the second mode is switched according to high level or low level of the one setting signal which is input to the logic setting terminal.

2. The drive signal output circuit according to claim 1 , wherein

the output circuit is an H bridge circuit in which two series connections, each of two transistors, are placed between a power supply line and a ground line, and intermediate points of the series connections are a pair of outputs.

3. The drive signal output circuit according to claim 1 , wherein

the drive signal output circuit is formed in a driver chip placed on a board, a power supply pad and a ground pad are placed on the driver chip, and the logic setting terminal of the driver chip is connected to one of a lead connected to a power supply pad and a lead connected to a ground pad, so that the logic setting signal is set to an H level or an L level.

4. A multi-chip package, comprising:

a driver chip having a drive signal output circuit comprising:

a signal input terminal to which two input signals are input,

a logic circuit to which the two input signals from the signal input terminal are input and which outputs a plurality of control signals corresponding to four states created by high level and low level of the two input signals;

an output circuit which includes a plurality of transistors which are controlled by the plurality of control signals, and which outputs a drive signal for driving a load, the drive signal corresponding to states of the plurality of transistors, and

a logic setting terminal to which a setting signal is input, wherein the setting signal assumes either high level or low level,

the plurality of control signals have:

a first mode for controlling the plurality of transistors of the output circuit to generate four states in accordance with the four states of the input signals, wherein the generated four states include a state in which a current is supplied to the load in a forward direction, a state in which a current is supplied to the load in a backward direction, a state in which the terminals of the load are isolated, and a state in which the terminals of the load are short-circuited; and

a second mode for controlling the plurality of transistors of the output circuit to generate three states in accordance with the four states of the input signals, wherein the generated three states include a state in which a current is supplied to the load in a forward direction, a state in which a current is supplied to the load in a backward direction, and a state in which the terminals of the load are isolated, and

wherein, in the logic circuit, whether to generate the plurality of control signals of the first mode or to generate the plurality of control signals of the second mode is switched according to high level or low level of the one setting signal which is input to the logic setting terminal, wherein

the driver chip and the logic chip are formed on a board, a pad which outputs the logic setting signal in the logic chip and a pad on the board are connected by a wire bonding, the pad and the logic setting terminal of the driver chip are connected by a wire bonding, and logic of the logic circuit of the driver chip is switched by the logic setting signal from the logic chip.

5. The multi-chip package according to claim 4 , wherein

the drive signal output circuit is formed in the driver chip placed on the board, a power supply pad and a ground pad are provided in the driver chip, and the logic setting terminal of the driver chip is connected to one of a lead connected to the power supply pad and a lead connected to the ground pad, so that the logic setting signal is set to an H level or an L level.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →