Memory device including a programmable resistance element
View Patent ↗Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.
1. A method of refreshing a memory device comprising:
counting a number of times of read operation of the memory device, wherein the memory device comprising a plurality of memory cells, each of memory cells including a programmable resistance element;
issuing a refresh operating signal when the number of times of read operation has reached a predetermined value; and
refreshing all memory cells.
2. The method according to claim 1 , wherein counting a number of times of read operation is carried out by counting a number of times of read command being input to a command input circuit of the memory device.
3. The method according to claim 1 , wherein the programmable resistance element comprises a phase change material.
4. The method according to claim 1 , further comprising: holding high/low resistance data transferred from each of the memory cells by using a data register at the time of refreshing.
5. The method according to claim 4 , further comprising:
setting all memory cells of a refresh unit to low resistance state after holding high/low resistance data by the data register;
referring to high/low resistance data of each of memory cells, wherein the high/low resistance data are holding by the data register; and
setting memory cells which respond to holding high resistance in the data register to high resistance state.
6. The method according to claim 4 , further comprising:
setting all memory cells of a refresh unit to high resistance state after holding high/low resistance data by the data register;
referring to high/low resistance data of each of memory cells, wherein the high/low resistance data are holding by the data register; and
setting memory cells which respond to holding low resistance in the data register to low resistance state.
7. The method according to claim 1 , further comprising: detecting a data write state in each of the memory cells at the time of refreshing by using a verification amplifier.
8. The method according to claim 7 , wherein the verification amplifier compares a resistance of each of the memory cells with a predetermined resistance value at the time of refreshing.
9. A method of refreshing a memory device comprising:
storing data to memory cells based on a high/low resistance of each of the memory cells;
applying a first stress to a first dummy cell which monitors a high resistance of the memory cells, wherein the first stress is same as a current stress being applied to one of the memory cells which is set to the high resistance;
applying a second stress to a second dummy cell which monitors a low resistance of the memory cells, wherein the second stress is same as a current stress being applied to one of the memory cells which is set to the low resistance; and
issuing a refresh operating signal in response to a change of the resistance of the first dummy cell or the second dummy cell; and
refreshing the memory cells, the first dummy cell and the second dummy cell.
10. The method according to claim 9 , wherein the high/low resistance of the memory cell corresponds to a change in the crystal state of a phase change material.
11. The method according to claim 9 , wherein the refresh operating signal is issued when the resistance of the first dummy cell is out of a predetermined first value or the resistance of the second dummy cell is out of a predetermined second value.
12. The method according to claim 9 , wherein the first dummy cell, the second dummy cell and the memory cells which monitored by both the first dummy cell and the second dummy cell are selected by a same word line at the time of write and read operation.
13. The method according to claim 9 , further comprising: holding high/low resistance data transferred from each of the memory cells by using a data register at the time of refreshing.
14. The method according to claim 13 , further comprising:
setting all memory cells of a refresh unit to low resistance state after holding high/low resistance data by the data register;
referring to high/low resistance data of each of memory cells, wherein the high/low resistance data are holding by the data register; and
setting memory cells which respond to holding high resistance in the data register to high resistance state.
15. The method according to claim 13 , further comprising:
setting all memory cells of a refresh unit to high resistance state after holding high/low resistance data by the data register;
referring to high/low resistance data of each of memory cells, wherein the high/low resistance data are holding by the data register; and
setting memory cells which respond to holding low resistance in the data register to low resistance state.
16. The method according to claim 9 , further comprising:
detecting a data write state in each of the memory cells at the time of refreshing by using a verification amplifier.
17. The method according to claim 16 , wherein the verification amplifier compares a resistance of each of the memory cells with a predetermined resistance value at the time of refreshing.