IP Library Granted Patent US 8,053,906
Granted Patent B2
US 8,053,906 · App. 12/501,285 · Granted Nov 8, 2011

Semiconductor package and method for processing and bonding a wire

Assignee: Advanced Semiconductor Engineering, Inc.
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Quick Facts
Patent No.
US 8,053,906
App. No.
12/501,285
Granted
Nov 8, 2011
Kind
B2
Abstract

A copper bonding wire includes a line portion and a non-spherical block portion. The non-spherical block portion is physically connected to the line portion, and the cross-sectional area of the non-spherical block portion is bigger than that of the line portion.

Claims (38)

1. A semiconductor package comprising:

a carrier;

a chip disposed on the carrier, wherein the chip has a first surface and a second surface opposite to the first surface;

a pad disposed on the first surface of the chip;

a copper bonding wire comprising:

a line portion; and

a non-spherical block portion physically connected to the line portion, wherein the cross-sectional area of the non-spherical block portion is bigger than that of the line portion, the non-spherical block portion is bonded to the pad, and the bonding interface between the pad and the non-spherical block portion is a non-circular cross-section, and wherein the non-spherical block portion has a bottom surface provided with at least one first pattern, and the first pattern has a saw-toothed cross-section; and

a molding compound for sealing the chip and the copper bonding wire and covering the carrier.

2. The semiconductor package as claimed in claim 1 , wherein the bonding interface between the pad and the non-spherical block portion is the non-circular cross-section, which includes two straight lines and two curved lines.

3. The semiconductor package as claimed in claim 1 , wherein the bonding interface between the pad and the non-spherical block portion is the non-circular cross-section, which includes four straight lines and four curved lines.

4. The semiconductor package as claimed in claim 1 , wherein the pad has a top surface provided with at least one second pattern which is bonded to the first pattern.

5. The semiconductor package as claimed in claim 4 , wherein the second pattern has a saw-toothed cross-section.

6. The semiconductor package as claimed in claim 4 , wherein the hardness of the non-spherical block portion of the copper bonding wire is more than that of the pad.

7. A semiconductor package comprising:

a carrier;

a chip disposed on the carrier, wherein the chip has a first surface and a second surface opposite to the first surface;

a pad disposed on the first surface of the chip;

a copper bonding wire comprising:

a line portion; and

a non-spherical block portion physically connected to the line portion, wherein the cross-sectional area of the non-spherical block portion is bigger than that of the line portion, the non-spherical block portion is bonded to the pad, and the bonding interface between the pad and the non-spherical block portion is a non-circular cross-section; and

a molding compound for sealing the chip and the copper bonding wire and covering the carrier,

wherein the non-spherical block portion has a rough bottom surface.

8. The copper bonding wire as claimed in claim 1 , wherein the non-spherical block portion has two flat side surfaces.

9. The copper bonding wire as claimed in claim 8 , wherein the non-circular cross-section of the non-spherical block portion includes two straight lines and two curved lines.

10. The copper bonding wire as claimed in claim 1 , wherein the non-spherical block portion has four flat side surfaces.

11. The copper bonding wire as claimed in claim 10 , wherein the non-circular cross-section of the non-spherical block portion includes four straight lines and four curved lines.

12. A method for processing a copper bonding wire comprising the following steps of:

providing a copper bonding wire comprising a line portion and a block portion, wherein the block portion is physically connected to the line portion, and the cross-sectional area of the block portion is bigger than that of the line portion; and

pressing the block portion on a patterned surface of an external tool so as to form a non-spherical block portion that has a bottom surface provided with at least one pattern, wherein the pattern has a saw-toothed cross-section.

13. The method as claimed in claim 12 , wherein the patterned surface of the external tool has a non-adhesive surface.

14. The method as claimed in claim 12 , wherein the formation of the non-spherical block portion comprises:

clipping the block portion for being deformed to a non-spherical block portion by a clipping process.

15. The method as claimed in claim 12 , wherein the formation of the non-spherical block portion comprises:

moving the block portion for contacting an interior of an external mold, whereby the block portion is deformed to a non-spherical block portion.

16. The method as claimed in claim 12 , wherein the hardness of the block portion of the copper bonding wire is less than that of the external tool.

17. The semiconductor package as claimed in claim 1 , wherein the pad has a rectangular shape defined by two first longitudinal sides and two first traverse sides, the non-circular cross-section has a shape defined by two second longitudinal sides and two second curved sides, and the first longitudinal sides are parallel to the second longitudinal sides.

18. The semiconductor package as claimed in claim 1 , wherein the pad has a rectangular shape defined by two first longitudinal sides and two first traverse sides, the non-circular cross-section has a shape at least defined by two second longitudinal sides and two second traverse sides, the first longitudinal sides are parallel to the second longitudinal sides, and the first traverse sides are parallel to the second traverse sides.

19. The semiconductor package as claimed in claim 18 , wherein the non-circular cross-section has the shape further defined by four curved sides, each the curved side connects with one of the second longitudinal sides and with one of the second traverse sides.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2009
From: CHANG, HSIAO CHUAN; TSAI, TSUNG YUEH; LAI, YI SHAO; TONG, HO MING; CHEN, JIAN CHENG; YIH, WEI CHI; HUNG, CHANG YING; HSU, CHENG TSUNG; HUNG, CHIH CHENG
To: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Reel/Frame 022942/0594 →
Priority Claims (1)
TW 97133402 A · Sep 1, 2008 · national
Continuity (2)
Provisional Application 61079811 · Jul 11, 2008
Related Publication 20100007009A1 · Jan 14, 2010