Method of forming micro pattern in semiconductor device

1. A method of forming a micro pattern in a semiconductor device, the method comprising:

forming an target layer, a hard mask layer and first sacrificial patterns over a semiconductor substrate on which a cell gate region, a selective transistor region and a periphery circuit region are defined;

forming an insulating layer and a second sacrificial layer on the hard mask layer and the first sacrificial patterns;

removing the insulating layer and the second sacrificial layer formed in the selective transistor region and the periphery circuit region;

performing a first etch process so as to allow the second sacrificial layer formed in the cell gate region to remain on the insulating layer between the first sacrificial patterns for forming second sacrificial patterns;

removing the insulating layer placed on the first sacrificial patterns and between the first and second sacrificial patterns in the cell gate region;

etching the hard mask layer using a second etch process utilizing the first and second sacrificial patterns as the etch mask to form a hard mask pattern; and

etching the target layer using a third etch process utilizing the hard mask pattern as the etch mask.

2. The method of claim 1 , wherein the target layer is formed of a tungsten silicide (WSi x ) layer.

3. The method of claim 1 , wherein a stack structure includes a tunnel insulating layer, a first conductive layer for a floating gate, a dielectric layer and a second conductive layer for a control gate formed between the target layer and the semiconductor substrate.

4. The method of claim 3 , wherein the tunnel insulating layer, the first conductive layer for the floating gate, the dielectric layer and the second conductive layer for the control gate formed between the target layer and the semiconductor substrate are etched to form the gate when the third etch process is performed.

5. The method of claim 1 , wherein the hard mask layer has a stack structure including an amorphous carbon layer and a silicon oxynitride (SiON) layer.

6. The method of claim 1 , wherein the first sacrificial layer is formed of a polysilicon layer, a silicon oxide (SiO 2 ) layer, a tungsten layer or a SOG (spin on glass) layer.

7. The method of claim 1 , wherein the first sacrificial pattern has a critical dimension that is approximately half of a pitch of patterns defined by the target layer as a result of the third etch process.

8. The method of claim 1 , wherein the insulating layer is formed from amorphous carbon layer, silicon oxide (SiO 2 ), a tungsten (W) or a SOG (spin on glass).

9. The method of claim 1 , wherein the insulating layer is formed from material having an etch selectivity with respect to material utilized for forming the second sacrificial layer and the first sacrificial pattern.

10. The method of claim 1 , wherein the insulating layer deposited on a side surface of the first sacrificial pattern has a thickness that is approximately half of a pitch of patterns defined by the target layer as a result of the third etch process.

11. The method of claim 1 , wherein the second sacrificial layer is formed from conductive material or insulative material.

12. The method of claim 1 , wherein the second sacrificial layer is formed of a SOG (spin on glass) layer, an organic bottom anti-reflective coating containing silicon such as a multi-functional hard mask layer, a silicon oxide (SiO 2 ) layer, a tungsten (W) layer or a polysilicon layer.

13. The method of claim 12 , further comprising performing a heat treatment process after forming the deposition process if SOG material is utilized.

14. The method of claim 1 , wherein the second sacrificial layer is removed through a dry etch process utilizing the insulating layer as an etch stop layer when a process for removing the second sacrificial layer formed in the selective transistor region and the peripheral region is performed.

15. The method of claim 1 , wherein the insulating layer is removed through a dry etch process utilizing the hard mask layer as an etch stop layer when a process for removing the insulating layer formed in the selective transistor region and the peripheral region is performed.

16. The method of claim 1 , wherein the second sacrificial layer remained in the selective transistor region is removed when a process for removing the second sacrificial layer remained in the cell gate region is performed.

17. The method of claim 16 , wherein the second sacrificial layer remained on the selective transistor region is removed through the etchback process.

18. The method of claim 1 , wherein the second sacrificial pattern is leveled with the first sacrificial pattern when the first etch process is performed.

19. The method of claim 1 , wherein the insulating layer has an etch selectivity with respect to material utilized for forming the first sacrificial pattern and the second sacrificial layer when the first etch process and the process for removing the insulating layer are performed.

20. The method of claim 1 , wherein the insulating layer remained in the selective transistor region is removed when a process for removing the insulating layer remained in the cell gate region is performed.

21. The method of claim 20 , wherein the insulating layer remained on the selective transistor region is removed through a dry etch process utilizing oxygen (O 2 ) plasma.

22. The method of claim 1 , wherein the second sacrificial pattern is formed between the first sacrificial patterns.

23. The method of claim 1 , wherein the second etch process is a dry etch process.