Granted Patent B2

US 9,030,895 · App. 12/510,633 · Granted May 12, 2015

Abstract

Claims (71)

1. A system, comprising:

a memory including a data signal line and a data synchronization signal line; and

an information processing device which performs a data communication to and from the memory via the data signal line,

wherein the memory includes a setting module configured to store mode information, wherein the mode information determines whether the data signal line is set to be a data signal line for common input/output use in a first mode, a data signal line for output-only use in a second mode, or a data signal line for input-only use in a third mode, and wherein the mode information further determines whether the data synchronization signal line is set to be a data synchronization signal line for common input/output use in the first mode, a data synchronization signal line for output only use in the second mode, or a data synchronization signal line for input only use in the third mode;

wherein the information processing device provides a data signal line set command the mode information, wherein the data signal line set command instructs the memory to load the mode information into the setting module for specifying one of the first mode, the second mode, and the third mode corresponding to a type of the data communication before performing the data communication; and

wherein the memory sets the data signal line and the data synchronization signal line into the one of the first mode, the second mode, and the third mode based at least in part on the mode information stored in the setting module, and performs the data communication based on the set of commands by using the data signal line set in the one of the first mode, the second mode, and the third mode.

2. The system as claimed in claim 1 ,

wherein the memory includes a first data line, and a second data line;

the memory further comprising;

an input buffer coupled between the data signal line and the first data line;

an output buffer coupled between the data signal line and the second data line; and

wherein the setting module controls enabling/disenabling the input buffer and the output buffer based at least in part on the mode information.

3. The system as claimed in claim 1 , the memory further comprising: a plurality of data buffers each including an input buffer and an output buffer to perform the data communication,

wherein the input buffers of the plurality of data buffers are activated and the output buffers of the plurality of data buffers are activated when the first mode is set so that a continuous read or write operation is performed by using the activated output buffers or input buffers, respectively.

4. The system as claimed in claim 3 ,

wherein the plurality of data buffers includes a first group of data buffers and a second group of data buffers, and

wherein the input buffers of the first group of data buffers are activated and the output buffers of the first group of data buffers are inactivated, and the input buffers of the second group of data buffers are inactivated and the output buffers of the second group of data buffers are activated, when the second mode is set and when the third mode is set, so that a real operation is performed by using the output buffers of the second group and a write operation is performed by using the input buffers of the first group, independently.

5. The system as claimed in claim 1 ,

wherein the memory further includes a read synchronization line, and a write synchronization line;

the memory further comprising:

an input buffer coupled between the data synchronization signal line and the read synchronization line:

an output buffer coupled between the data synchronization signal line and the third write synchronization line; and

wherein the setting module controls enabling/disenabling the input buffer and the output buffer based at least in part on the synchronization mode information.

6. A system, comprising:

a memory including a data signal line and a data-synchronization signal line; and

an information processing device which performs a data communication to and from the memory via the data signal line,

wherein said memory includes:

a register which retains a setting information that determines whether the data signal line is set to be a data signal line for common input/output use in a first mode, a data signal line for output-only use in a second mode, or a data signal line for input only use in a third mode, and wherein the setting information also determines whether data-synchronization signal line is set to be a data-synchronization signal line for common input/output use in the first mode, a data-synchronization signal line for output only use in the second mode, or a data-synchronization signal line for input only use in the third mode, and

a setting module which sets the data signal line and the data-synchronization signal line into the one of the first mode, the second mode, and the third mode according to the setting information retained in the register,

wherein the information processing device issues a set of commands for performing the data communication, a data signal line set command, and the setting information, wherein the data signal line set command causes the memory to store the setting information in the register; and

wherein the memory sets the data signal line and the data-synchronization signal in into the one of the first mode, the second mode, and the third mode based at least in part on the setting information in the register, and performs the data communication based on the set of commands by using the data signal line set in the one of the first mode, the second mode, and the third mode.

7. The system as claimed in claim 6 , the memory further comprising:

a command decoder configured to receive the data-signal-line set command to output an instruction;

an address buffer configured to receive bits of an address signal; and

a controller configured to set the bits of the address signal as the setting information in the register responsive to the instruction.

8. The system as claimed in claim 7 ,

wherein the memory includes a first data line, and a second data line;

the memory further comprising:

an input buffer coupled between the data signal line and the first data line;

an output buffer coupled between the data signal line and the second data line; and wherein the setting module controls enabling/disenabling the input buffer and the output buffer, based on the bits of the register.

9. The system as claimed in claim 7 , the memory further comprising:

a plurality of data buffers each including an input buffer and an output buffer to perform the data communication,

wherein the input buffers of the plurality of data buffers are activated and the output buffers of the plurality of data buffers are activated, based on the bits of address signal, when the first mode is set, so that a continuous read or write operation is performed by using the output buffers or the input buffers, respectively.

10. The system as claimed in claim 9 ,

wherein the plurality of data buffers includes a first group of data buffers and a second group of data buffers, and

wherein, the input buffers of the first group of data buffers are activated and the output buffers of the first group of data buffers are inactivated, and the input buffers of the second group of data buffers are inactivated and the output buffers of the second group of data buffers are activated, based on the bits of address signal, when the second mode is set and when the third modes is set, so that a read operation is performed by using the output buffers of the second group and a write operation is performed by using the input buffers of the first group, independently.

11. The system as claimed in claim 6 , wherein the memory is a Double Data Rate-Synchronous Dynamic Random Access Memory.

12. The system as claimed in claim 6 ,

wherein the memory further includes a read synchronization line, and a write synchronization line,

the memory further comprising;

an input buffer coupled between the data-synchronization signal line and the read synchronization line;

an output buffer coupled between the data-synchronization signal line and the write synchronization line; and

wherein the setting module controls enabling/disenabling the input buffer and the output buffer based on the setting information of the register.

13. A method of transmitting a data on a plurality of data signal lines in a semiconductor storage device, the method comprising;

transmitting a first data as the data in response to continuously receiving read instructions;

transmitting a second data as the data in response to continuously receiving write instructions;

transmitting third and fourth data as the data in response to alternatively receiving read and write instructions;

before transmitting the first data, setting each of the plurality of data signal lines to be a data signal line for common input/output use and setting a data synchronization line to be a data synchronization signal line for common input/output use, so that the first data is read out from the semiconductor storage device by using the plurality of data signal lines each of which has been set for the common input/output use in response to the continuous read instructions;

before transmitting the second data, setting each of the plurality of data signal lines to be a data signal line for common input/output use and setting the data synchronization line to be a data synchronization signal line for common input/output use, so that the second data is written to the semiconductor storage device by using the plurality of data signal lines each of which has been set for the common input/output use in response to the continuous write instructions; and

before transmitting the third data, setting a first group of the plurality of data signal lines each to be a data signal line for input only use and a second group of the plurality of data signal lines each to be a data signal line for output only use and setting the data-synchronization signal line corresponding to the first group to be a data-synchronization signal for input only use, and setting the data-synchronization signal line corresponding to the second group to be a data-synchronization signal for output only use, so that the third data is written to the semiconductor storage device by using the first group of the plurality of data signal lines each of which has been set for input only use in response to the write instruction and the fourth data is read out from the semiconductor storage device by using the second group of the plurality of data signal lines each of which has been set for output only use in response to the read instruction, independently.

14. The method as claimed in claim 13 , the method further comprising:

before transmitting one of the first data, the second data, the third data, and the fourth data, receiving a command for setting the plurality of data signal lines and bits of address signal specifying a type to which the plurality of data signal lines are set.

15. The method as claimed in claim 14 , the method further comprising:

decoding the command to produce a decoded command;

storing the bits of address signal into a register in response to the decoded command; and

setting the plurality of data signal lines to be the data signal line for common input/output use, the data signal line for output-only use, or the data signal line for input-only use, based on the bits.

16. The method as claimed in claim 13 ,

wherein the plurality of data signal lines each includes a data buffer including an input buffer and an output buffer;

wherein the setting each of the plurality of data signal lines to be a data signal line for common input/output use comprises: activating the input buffers of the plurality of data buffers and the output buffers of the plurality of data buffers; and

wherein the setting the first group of the plurality of data signal lines each to be the data signal line for input-only use and the second group of the plurality of data signal lines each to be the data signal line for output-only use comprises:

activating the input buffers of the first group of the data buffers and inactivating the output buffers of the first group of the data buffers, and inactivating the input buffers of the second group of the data buffers and activating the output buffers of the second group of the data buffers.

Assignments (9)