IP Library Granted Patent US 8,143,696
Granted Patent B2
US 8,143,696 · App. 12/516,301 · Granted Mar 27, 2012

Integrated circuit inductors with reduced magnetic coupling

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Quick Facts
Patent No.
US 8,143,696
App. No.
12/516,301
Granted
Mar 27, 2012
Kind
B2
Abstract

An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.

Claims (30)

1. An integrated circuit inductor structure, comprising:

a first inductor element formed on a semiconductor substrate, the first inductor element having a first effective magnetic field direction associated therewith; and

at least a second inductor element formed on the semiconductor substrate proximate the first inductor element, the second inductor element having a second effective magnetic field direction associated therewith, the first and second inductor elements being oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions;

wherein at least one of the first and second inductor elements comprises a plurality of conductive loops in which a first conductive loop partially but not completely overlaps at least a second conductive loop.

2. The inductor structure of claim 1 , wherein the angle between the first and second effective magnetic field directions is substantially equal to ninety degrees.

3. The inductor structure of claim 1 , wherein each of the first and second inductor elements comprises one or more individual turns on a same inductor structure.

4. The inductor structure of claim 1 , wherein each of the first and second inductor elements comprises a spiral inductor having a directed magnetic field.

5. The inductor structure of claim 1 , wherein centers of respective ones of the plurality of conductive loops are arranged along an arc.

6. The inductor structure of claim 1 , wherein centers of respective ones of the plurality of conductive loops are arranged along a line slanted relative to the respective ones of the plurality of conductive loops.

7. The inductor structure of claim 1 , wherein any two adjacent conductive loops in the at least one inductor element are formed in different respective conductive layers in the integrated circuit.

8. The inductor structure of claim 1 , wherein the conductive loops in the at least one inductor element are substantially circular.

9. The inductor structure of claim 1 , wherein each of the first and second inductor elements is vertically oriented.

10. The inductor structure of claim 1 , wherein the first conductive loop and the second conductive loop are of different sizes.

11. The inductor structure of claim 10 , wherein the first conductive loop and the second conductive loop are concentric.

12. The inductor structure of claim 1 , wherein the first conductive loop and the second conductive loop are not concentric.

13. The inductor structure of claim 12 , wherein the first conductive loop and the second conductive loop are of substantially equal size.

14. An electronic system, comprising:

at least one integrated circuit including at least one inductor structure, the at least one inductor structure comprising:

a first inductor element formed on a semiconductor substrate, the first inductor element having a first effective magnetic field direction associated therewith; and

at least a second inductor element formed on the semiconductor substrate proximate the first inductor element, the second inductor element having a second effective magnetic field direction associated therewith, the first and second inductor elements being oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions;

wherein at least one of the first and second inductor elements comprises a plurality of conductive loops in which a first conductive loop partially but not completely overlaps at least a second conductive loop.

15. The system of claim 14 , wherein each of the first and second inductor elements comprises one or more individual turns on a same inductor structure.

16. The system of claim 14 , wherein each of the first and second inductor elements comprises a spiral inductor having a directed magnetic field.

17. The system of claim 14 , wherein centers of respective ones of the plurality of conductive loops are arranged along an arc.

18. The system of claim 14 , wherein centers of respective ones of the plurality of conductive loops are arranged along a line slanted relative to the respective ones of the plurality of conductive loops.

19. The system of claim 14 , wherein the conductive loops in the at least one inductor element are substantially circular.

20. A method of reducing magnetic coupling between at least two integrated circuit inductors, the method comprising the steps of:

forming a first inductor element on a semiconductor substrate, the first inductor element having a first effective magnetic field direction associated therewith; and

forming at least a second inductor element on the semiconductor substrate proximate the first inductor element, the second inductor element having a second effective magnetic field direction associated therewith, the first and second inductor elements being oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions;

wherein at least one of the first and second inductor elements comprises a plurality of conductive loops in which a first conductive loop partially but not completely overlaps at least a second conductive loop.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035059/0001 →
MERGER Recorded Feb 20, 2015
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 035058/0895 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2009
From: MAO, WEIWEI; MOINIAN, SHAHRIAR; PAIST, KENNETH WADE; WILSON, WILLIAM B.
To: AGERE SYSTEMS INC.
Reel/Frame 022734/0944 →