Field effect transistor with trench-isolated drain
View Patent ↗A MOS transistor includes a body region of a first conductivity type, a conductive gate and a first dielectric layer, a source region of a second conductivity type formed in the body region, a heavily doped source contact diffusion region formed in the source region, a lightly doped drain region of the second conductivity type formed in the body region where the lightly doped drain region is a drift region of the MOS transistor, a heavily doped drain contact diffusion region of the second conductivity type formed in the lightly doped drain region; and an insulating trench formed in the lightly doped drain region adjacent the drain contact diffusion region. The insulating trench blocks a surface current path in the drift region thereby forming vertical current paths in the drift region around the bottom surface of the trench.
1. A metal-oxide-semiconductor (MOS) transistor, comprising:
a body region of a first conductivity type formed in a semiconductor layer;
a conductive gate formed on a first surface of the semiconductor layer and insulated from the semiconductor layer by a gate dielectric layer;
a source region of a second conductivity type formed in the body region of the semiconductor layer on one side of the conductive gate, a part of the source region extending underneath the conductive gate;
a heavily doped source contact diffusion region of the second conductivity type formed in the source region, the source contact diffusion region forming the source terminal of the MOS transistor;
a lightly doped drain region of the second conductivity type formed in the body region of the semiconductor layer on the opposite side of the conductive gate, the lightly doped drain region being a drift region of the MOS transistor and a part of the lightly doped drain region extending underneath the conductive gate;
a heavily doped drain contact diffusion region of the second conductivity type formed in the lightly doped drain region, the drain contact diffusion region forming the drain terminal of the MOS transistor; and
an insulating trench formed in the lightly doped drain region adjacent the drain terminal, the insulating trench blocking a surface current path in the drift region thereby forming vertical current paths in the drift region around a bottom surface of the trench,
wherein the insulating trench comprises a dielectric sidewall and the conductive gate extends into and filling remaining portion of the trench, the dielectric sidewall having a thickness greater than the gate dielectric layer.
2. The MOS transistor of claim 1 , further comprising a heavily doped body contact diffusion region of the first conductivity type formed in the body region.
3. The MOS transistor of claim 1 , wherein the insulating trench is formed in the lightly doped drain region adjacent the drain terminal.
4. The MOS transistor of claim 1 , wherein the insulating trench is formed in the lightly doped drain region spaced apart from the drain terminal.
5. The MOS transistor of claim 1 , wherein the dielectric sidewall of the insulating trench comprises a silicon oxide layer.
6. The MOS transistor of claim 1 , wherein the semiconductor layer comprises an epitaxial layer of the first conductivity type.
7. The MOS transistor of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.
8. The MOS transistor of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.
9. The MOS transistor of claim 1 , wherein the dielectric sidewall of the insulating trench comprises portions protruding above the first surface of the semiconductor layer.
10. The MOS transistor of claim 1 , wherein the conductive gate comprises a polysilicon layer, the polysilicon layer of the conductive gate extending over the portions of the dielectric sidewall protruding above the first surface to fill the remaining portion of the trench.