Semiconductor device and power converter using the same
A semiconductor device which can avoid increase of a conduction loss of an IGBT, secure a low noise characteristic and also reduce a switch loss. The switching device is of a trench gate type, in which a drift n − layer 110 is exposed to its main surface to a floating p layer 126 and to trench gates. In other words, the floating p layer 126 is provided within the drift n − layer 110 to be spaced from the trench gates.
1. A semiconductor device comprising:
a semiconductor substrate having a pair of main surfaces;
a first semiconductor region of a first conductivity type positioned adjacent to one of the main surfaces of the semiconductor substrate and located within the semiconductor substrate;
a second semiconductor region of a second conductivity type provided adjacent to the first semiconductor region and having a carrier concentration lower than a carrier concentration of the first semiconductor region;
a third semiconductor region of the second conductivity type provided adjacent to the second semiconductor region and having a carrier concentration lower than the carrier concentration of the second semiconductor region;
a plurality of MOS type trench gates extended from one of the main surfaces of the semiconductor substrate into the third semiconductor region to have at least two sorts of different intervals;
a fourth semiconductor region of the first conductivity type provided between the MOS type trench gates having a narrow adjacent interval and having a carrier concentration higher than the carrier concentration of the third semiconductor region;
a fifth semiconductor region of the second conductivity type provided between the MOS type trench gates having the narrow adjacent interval, located within the fourth semiconductor region to be adjacent to the MOS type trench gates, and having a carrier concentration higher than the carrier concentration of the fourth semiconductor region;
a sixth semiconductor region of the first conductivity type located between the MOS type trench gates having an adjacent interval larger than the narrow interval and having a carrier concentration higher than the carrier concentration of the third semiconductor region;
a first electrode located between the MOS type trench gates having the narrow adjacent interval to be contacted with the fourth and fifth semiconductor regions; and
a second electrode contacted with the first semiconductor region,
wherein the sixth semiconductor region extends from one main surface of the semiconductor substrate into the third semiconductor region and is exposed at a part of the one main surface,
the third semiconductor region is exposed at the part of the one main surface, between the sixth semiconductor region and the trench gate, and includes a part which extends from the part of the one main surface into the semiconductor substrate, and
the sixth semiconductor region and the trench gate are isolated by the part of the third semiconductor region.
2. A semiconductor device according to claim 1 , wherein the sixth semiconductor region is spaced from the trench gates by a distance not larger than 10 μm.
3. A semiconductor device according to claim 1 , wherein the sixth semiconductor region is deeper than the fourth semiconductor region.
4. A semiconductor device according to claim 1 , wherein the fourth semiconductor region is formed to cover a lower side of the trench gates.
5. A semiconductor device according to claim 1 , further comprising:
a seventh semiconductor region of the second conductivity type which is provided between the MOS type trench gates having the adjacent narrow interval, located between the third and fourth semiconductor regions to be adjacent to the MOS type trench gates, and has a carrier concentration higher than the carrier concentration of the third semiconductor region.
6. A semiconductor device according to claim 5 , further comprising:
an eighth semiconductor region of the first conductivity type which is located between the third and seventh semiconductor regions, contacted with the MOS type trench gates, and has a carrier concentration higher than the carrier concentration of the third semiconductor region.
7. A semiconductor device according to claim 1 , wherein the sixth semiconductor region is contacted with the first electrode directly or through a resistance.
8. A power converter comprising:
a pair of DC terminals;
AC terminals corresponding in number to phases of an AC source; and
a plurality of power conversion units connected between the pair of DC terminals,
wherein each of the power conversion units has a series circuit of two parallel circuits each having a switching element and a diode of a polarity opposite to the switching element, the power conversion units have the AC terminals as different mutual interconnection points between the two parallel circuits, and the switching element is the semiconductor device set forth in claim 1 .