IP Library Granted Patent US 8,148,788
Granted Patent B2
US 8,148,788 · App. 12/538,635 · Granted Apr 3, 2012

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 8,148,788
App. No.
12/538,635
Granted
Apr 3, 2012
Kind
B2
Abstract

The invention is directed to reduction of a manufacturing cost and enhancement of a breakdown voltage of a PN junction portion abutting on a guard ring. An N− type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An insulation film is formed on the P type semiconductor layer. Then, a plurality of grooves, i.e., a first groove, a second groove and a third groove are formed from the insulation film to the middle of the N− type semiconductor layer in the thickness direction thereof. The plurality of grooves is formed so that one of the two grooves next to each other among these, that is closer to an electronic device, i.e., to an anode electrode, is formed shallower than the other located on the outside of the one. Then, an insulating material is deposited in the first groove, the second groove and the third groove. The lamination body of the semiconductor substrate and the layers laminated thereon is then diced along dicing lines.

Claims (43)

1. A semiconductor device comprising:

a semiconductor substrate;

a semiconductor layer formed on the semiconductor substrate;

an electronic device formed in the semiconductor layer; and

a guard ring formed in the semiconductor layer so as to surround the electronic device in plan view of the semiconductor device,

wherein the guard ring comprises a plurality of grooves formed in the semiconductor layer so as to surround the electronic device in the plan view of the semiconductor device, an insulating material is deposited in each of the grooves, the depths of the grooves are different from each other, and each of the grooves penetrates through the semiconductor layer, and

a first groove of the grooves is formed next to a second groove of the grooves, the electronic device is closer to the first groove than to the second groove, and the first groove is narrower than the second groove.

2. The semiconductor device of claim 1 , wherein the first groove is shallower than the second groove.

3. A semiconductor device comprising:

a semiconductor substrate;

a semiconductor layer formed on the semiconductor substrate;

an electronic device formed in the semiconductor layer; and

a guard ring formed in the semiconductor layer so as to surround the electronic device in plan view of the semiconductor device,

wherein the guard ring comprises a plurality of grooves formed in the semiconductor layer so as to surround the electronic device in the plan view of the semiconductor device, an insulating material is deposited in each of the grooves, the depths of the grooves are different from each other, and a first groove of the grooves is formed next to a second groove of the grooves, the electronic device is closer to the first groove than to the second groove, and the first groove is deeper than the second groove.

4. A semiconductor device comprising:

a semiconductor substrate;

a semiconductor layer formed on the semiconductor substrate;

an electronic device formed in the semiconductor layer; and

a guard ring formed in the semiconductor layer so as to surround the electronic device in plan view of the semiconductor device,

wherein the guard ring comprises a plurality of grooves formed in the semiconductor layer so as to surround the electronic device in the plan view of the semiconductor device, an insulating material is deposited in each of the grooves, the depths of the grooves are different from each other, and the insulating material fills each of the grooves at least partially so as to cover at least the semiconductor layer in each of the grooves, and extends outside the grooves so as to cover a portion of a top surface of the semiconductor layer.

5. A method of manufacturing a semiconductor device, comprising:

forming a semiconductor layer on a semiconductor substrate;

forming an electronic device in the semiconductor layer;

forming a plurality of grooves in the semiconductor layer so as to surround the electronic device in plan view of the semiconductor device and to penetrate through the semiconductor layer, the grooves having depths different from each other;

depositing an insulating material in each of the grooves to form a guard ring comprising the grooves having the insulating material therein; and

dicing the semiconductor substrate and the semiconductor layer along a dicing line provided outside the guard ring,

wherein a first groove of the grooves is formed next to a second groove of the grooves, the electronic device is closer to the first groove than to the second groove, and the first groove is narrower than the second groove.

6. The method of claim 5 , wherein the first groove is shallower than the second groove.

7. A method of manufacturing a semiconductor device, comprising:

forming a semiconductor layer on a semiconductor substrate;

forming an electronic device in the semiconductor layer;

forming a plurality of grooves in the semiconductor layer so as to surround the electronic device in plan view of the semiconductor device, the grooves having depths different from each other;

depositing an insulating material in each of the grooves to form a guard ring comprising the grooves having the insulating material therein; and

dicing the semiconductor substrate and the semiconductor layer along a dicing line provided outside the guard ring,

wherein a first groove of the grooves is formed next to a second groove of the grooves, the electronic device is closer to the first groove than to the second groove, and the first groove is deeper than the second groove.

8. A method of manufacturing a semiconductor device, comprising:

forming a semiconductor layer on a semiconductor substrate;

forming an electronic device in the semiconductor layer;

forming a plurality of grooves in the semiconductor layer so as to surround the electronic device in plan view of the semiconductor device, the grooves having depths different from each other;

depositing an insulating material in each of the grooves to form a guard ring comprising the grooves having the insulating material therein; and

dicing the semiconductor substrate and the semiconductor layer along a dicing line provided outside the guard ring,

wherein the insulating material fills each of the grooves at least partially so as to cover at least the semiconductor layer in each of the grooves, and extends outside the grooves so as to cover a portion of a top surface of the semiconductor layer.

9. The method of claim 5 , wherein the forming of the grooves in the semiconductor layer comprises a Bosch process.

Assignments (14)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2016
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038994/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2016
From: ON SEMICONDUCTOR NIIGATA CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 038988/0804 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CHANGE OF NAME Recorded Aug 11, 2015
From: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
To: ON SEMICONDUCTOR NIIGATA CO., LTD.
Reel/Frame 036327/0871 →
CHANGE OF NAME Recorded Aug 11, 2015
From: SANYO SEMICONDUCTOR CO., LTD.
To: SYSTEM SOLUTIONS CO., LTD
Reel/Frame 036300/0238 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER LISTED ON THE NAME CHANGE USP 7619299 PREVIOUSLY RECORDED ON REEL 025762, FRAME 0635 Recorded Jun 6, 2011
From: NIGATA SANYO ELECTRIC CO., LTD.
To: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 026424/0676 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 7619299, PREVIOUSLY RECORDED ON REEL 025762 FRAME 0320.ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT Recorded Jun 2, 2011
From: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
To: NIGATA SANYO ELECTRIC CO., LTD.
Reel/Frame 026654/0343 →
COMPANY SPLIT Recorded Dec 22, 2010
From: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
To: NIGATA SANYO ELECTRIC CO., LTD.
Reel/Frame 025762/0320 →
CHANGE OF NAME Recorded Dec 22, 2010
From: NIGATA SANYO ELECTRIC CO., LTD.
To: SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 025762/0635 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2009
From: SUZUKI, AKIRA; TSUCHIYA, NAOFUMI; KAMEYAMA, KOUJIRO
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.; SANYO SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 023100/0073 →