Input buffer circuit of semiconductor apparatus

1. An input buffer circuit of a semiconductor apparatus, comprising:

a first buffering unit configured to be activated by a voltage level difference between a source voltage terminal and a sink voltage terminal, generate a first compare signal and a second compare signal by comparing voltage levels of reference voltage and an input signal, and change voltage levels of the first compare signal and the second compare signal in response to an amount of current flowing between the sink voltage terminal and a ground terminal;

a control unit configured to control the voltage levels of the first and second compare signals in response to a voltage level difference between the reference voltage and the second compare signal; and

a second buffering unit configured to generate an output signal by comparing voltage levels of the input signal and the first compare signal.

2. The input buffer circuit of a semiconductor apparatus according to claim 1 , wherein the first buffering unit is configured to

generate the first compare signal at a lower voltage level than the voltage level of the second compare signal, when the voltage level of the input signal is higher than the level of the reference voltage, and

generate the first compare signal at a higher voltage level than the voltage level of the second compare signal, when the voltage level of the input signal is lower than the level of the reference voltage.

3. The input buffer circuit of a semiconductor apparatus according to claim 2 , wherein the control unit increases the amount of current flowing between the sink voltage terminal and a ground terminal, when the voltage level of the second compare signal is higher than the level of the reference voltage, and

decreases the amount of current flowing between the sink voltage terminal and the ground terminal, when the voltage level of the second compare signal is lower than the level of the reference voltage.

4. The input buffer circuit of a semiconductor apparatus according to claim 3 , wherein the control unit includes:

a control signal generator configured to generate a control signal in response to the second compare signal and the reference voltage; and

a current controller configured to increase or decrease the amount of current flowing between the sink voltage terminal and the ground terminal in response to a voltage level of the control signal.

5. The input buffer circuit of a semiconductor apparatus according to claim 4 , wherein the control signal generator is configured to generate the control signal by comparing the voltage level of the second compare signal with the level of the reference voltage.

6. The input buffer circuit of a semiconductor apparatus according to claim 2 , wherein the first buffering unit configured to include a fixed resistor increasing voltage levels of the first compare signal and the second compare signal by receiving external voltage through the source voltage terminal, and a voltage dropper decreasing the voltage levels of the first and second compare signals in response to the input signal and the reference voltage level.

7. The input buffer circuit of a semiconductor apparatus according to 6 , wherein the voltage dropper includes a signal voltage dropper configured to include a first transistor decreasing the voltage level of the first compare signal in response to the voltage level of the input signal and a second transistor decreasing the voltage level of the second compare signal in response to the level of the reference voltage,

wherein the control unit includes a control signal generator configured to increase a voltage level of a control signal, when the voltage level of the second compare signal becomes higher than the level of the reference voltage,

wherein the first transistor and the second transistor receive the voltage of the control signal as their back bias voltages, and

wherein the first compare signal is outputted from a node where the first transistor and the fixed resistor are coupled, the second compare signal is outputted from a node where the second transistor and the fixed resistor are coupled, and a node where the first transistor and the second transistor are coupled is the sink voltage terminal.

8. The input buffer circuit of a semiconductor apparatus according to 6 , wherein the voltage dropper includes the signal voltage dropper configured to include a first transistor that decreases the voltage level of the first compare signal in response to the voltage level of the input signal, a second transistor that decreases the voltage level of the second compare signal in response to the level of the reference voltage, and a third transistor that receives bias voltage through a gate, and having a drain coupled with the sink voltage terminal where sources of the first and second transistors are coupled and a source coupled with a ground terminal, and

wherein the control unit includes a control signal generator configured to increase a voltage level of a control signal, when the voltage level of the second compare signal becomes higher than the level of the reference voltage,

wherein the third transistor receives the voltage of the control signal as back bias voltage, and

wherein the first compare signal is outputted from a node where the first transistor and the fixed resistor are coupled, the second compare signal is outputted from a node where the second transistor and the fixed resistor are coupled.

9. The input buffer circuit of a semiconductor apparatus according to 1 , wherein the first and second compare signals are signals swinging between CML (Current Mode Logic) levels, and the output signal is a signal swinging between CMOS (Complementary Metal Oxide Semiconductor) levels.