FinFET formation with a thermal oxide spacer hard mask formed from crystalline silicon layer
A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer ( 19 ) that is isolated from an underlying first single crystal semiconductor layer ( 17 ) by a buried insulator layer ( 18 ); patterning and etching the second single crystal semiconductor layer ( 19 ) to form a single crystal mandrel ( 42 ) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers ( 52 ) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel ( 42 ) while substantially retaining the oxide spacers ( 52 ); and selectively etching the first single crystal semiconductor layer ( 17 ) using the oxide spacers ( 52 ) to form one or more FinFET channel regions ( 92 ).
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate structure comprising a first single crystal semiconductor layer over an underlying first insulator layer, and a second single crystal semiconductor layer over the first single crystal semiconductor layer that is isolated from the first single crystal semiconductor layer by an underlying second insulator layer;
patterning and etching the second single crystal semiconductor layer to form a single crystal patterned structure having vertical sidewalls;
oxidizing the single crystal patterned structure to grow oxide spacers on the vertical sidewalls of the single crystal patterned structure;
selectively removing any remaining portion of the single crystal patterned structure while substantially retaining the oxide spacers; and
selectively etching the first single crystal semiconductor layer using the oxide spacers as a mask to leave one or more FinFET channel regions patterned as per the oxide spacers.
2. The method of claim 1 , where providing the substrate structure comprises providing a double semiconductor-on-insulator substrate structure.
3. The method of claim 1 , where patterning and etching the second single crystal semiconductor layer comprises:
depositing a first hard mask layer over the second single crystal semiconductor layer;
patterning and etching the first hard mask layer to form a mandrel etch mask; and
selectively etching the second single crystal semiconductor layer using the mandrel etch mask to form the single crystal patterned structure having vertical sidewalls.
4. The method of claim 1 , where patterning and etching the second single crystal semiconductor layer comprises:
depositing a first nitride layer over the second single crystal semiconductor layer;
patterning and etching the first nitride layer to form a nitride hard mask on the second single crystal semiconductor layer; and
applying a reactive ion etch to selectively etch the second single crystal semiconductor layer using the nitride hard mask to form the single crystal patterned structure having vertical sidewalls.
5. The method of claim 4 , further comprising removing the nitride hard mask from the second single crystal semiconductor layer after oxidizing the single crystal patterned structure and before selectively removing any remaining portion of the single crystal patterned structure.
6. The method of claim 1 , where selectively removing any remaining portion of the single crystal patterned structure comprises applying a wet etch process to selectively remove any remaining portion of the single crystal patterned structure while substantially retaining the oxide spacers.
7. The method of claim 1 , where selectively removing any remaining portion of the single crystal patterned structure comprises applying a reactive ion etch process to selectively remove any remaining portion of the single crystal patterned structure while substantially retaining the oxide spacers.
8. The method of claim 1 , further comprising selectively removing any remaining portion of the underlying second insulator layer with a reactive ion etch process before selectively etching the first single crystal semiconductor layer.
9. The method of claim 1 , further comprising:
forming a gate layer over the FinFET channel regions, and
selectively etching the gate layer to form one or more gate electrodes over the FinFET channel regions.
10. A method for forming a plurality of FinFET structures on a semiconductor structure, comprising:
providing a substrate structure comprising:
a first crystalline semiconductor substrate layer,
a second crystalline semiconductor layer over at least part of the first semiconductor substrate layer and electrically isolated therefrom by a first insulator layer, and
a third crystalline semiconductor layer over at least part of the second crystalline semiconductor layer and electrically isolated therefrom by a second insulator layer;
selectively etching the third crystalline semiconductor layer to form a plurality of crystalline patterned semiconductor structures having a predetermined minimum pitch;
oxidizing the plurality of crystalline patterned semiconductor structures to grow a plurality of oxide sidewall spacers on the plurality of crystalline patterned semiconductor structures; and
selectively etching the second crystalline semiconductor layer using the plurality of oxide sidewall spacers directly or indirectly as an etch mask to form a plurality of FinFET channel regions having a minimum pitch that is less than the predetermined minimum pitch.
11. The method of claim 10 , where the first crystalline semiconductor layer comprises a bulk semiconductor substrate layer and the second crystalline semiconductor layer comprises an SOI crystalline semiconductor layer.
12. The method of claim 10 , where providing the substrate structure comprises providing a double semiconductor-on-insulator substrate structure.
13. The method of claim 10 , where selectively etching the third crystalline semiconductor layer comprises:
depositing a first hard mask layer over the third crystalline semiconductor layer;
patterning and etching the first hard mask layer to form a mandrel etch mask; and
selectively etching the third crystalline semiconductor layer using the mandrel etch mask to form the plurality of crystalline patterned semiconductor structures having the predetermined minimum pitch.
14. The method of claim 10 , where oxidizing the plurality of crystalline patterned semiconductor structures comprises thermally oxidizing the plurality of crystalline patterned semiconductor structures in a controlled thermal oxidation process to form oxide sidewall spacers, each having a predetermined thickness on the plurality of crystalline patterned semiconductor structures to form the plurality of oxide sidewall spacers.
15. The method of claim 10 , where the plurality of crystalline patterned semiconductor structures are formed to have equal line widths and spaces therebetween.
16. The method of claim 10 , where the plurality of FinFET channel regions are formed to have a thickness of about 8-10 nanometers.
17. The method of claim 10 , where selectively etching the third crystalline semiconductor layer comprises:
depositing a first nitride layer over the third crystalline semiconductor layer;
patterning and etching the first nitride layer to form a nitride hard mask on the third crystalline semiconductor layer; and
applying a reactive ion etch to selectively etch the third crystalline semiconductor layer using the nitride hard mask to form the plurality of crystalline patterned semiconductor structures having vertical sidewalls.
18. The method of claim 17 , further comprising removing the nitride hard mask from the third crystalline semiconductor layer after oxidizing the plurality of crystalline patterned semiconductor structures and before selectively etching the second crystalline semiconductor layer.
19. The method of claim 10 , further comprising
forming a gate insulator layer over the plurality of FinFET channel regions;
forming a conductive gate layer over the gate insulator layer; and
selectively etching the conductive gate layer to form a one or more FinFET gate electrodes.
20. A method for forming a FinFET structure, comprising:
providing a double semiconductor-on-insulator (SOI) substrate comprising a monocrystalline top SOI layer and a monocrystalline bottom SOI layer;
patterning and etching the monocrystalline top SOI layer to form an etch mask comprising a plurality of monocrystalline dummy structures having a predetermined minimum pitch;
thermally oxidizing the plurality of monocrystalline dummy structures to form uniform oxide sidewall spacers;
removing any remaining portion of the plurality of monocrystalline dummy structures while substantially retaining the uniform oxide sidewall spacers;
selectively etching the monocrystalline bottom SOI layer using the uniform oxide sidewall spacers as an etch mask to form a plurality of FinFET channel regions having a minimum pitch that is less than the predetermined minimum pitch;
forming a gate insulator layer over the plurality of FinFET channel regions;
forming a conductive gate layer over the gate insulator layer; and
selectively etching the conductive gate layer to form one or more FinFET gate electrodes.