Granted Patent B2

US 9,012,333 · App. 12/556,199 · Granted Apr 21, 2015

Abstract

Claims (39)

1. A method comprising:

forming a tunnel oxide layer on a substrate;

depositing via a first atomic layer deposition a first non-stoichiometric silicon nitride layer onto said tunnel oxide layer, said first non-stoichiometric silicon nitride layer comprises a first silicon richness value, said depositing comprises using a silicon precursor and a molecular nitrogen purge;

reducing said first silicon richness value by a predefined amount to produce a second silicon richness value;

depositing via a second atomic layer deposition a first silicon nitride layer above said first non-stoichiometric silicon nitride layer, said first silicon nitride layer comprises said second silicon richness value;

reducing said second silicon richness value by another predefined amount to produce a third silicon richness value; and

depositing via a third atomic layer deposition a second silicon nitride layer above said first silicon nitride layer, said second silicon nitride layer comprises said third silicon richness value.

2. The method of claim 1 , wherein said first silicon nitride layer is in contact with said first non-stoichiometric silicon nitride layer.

3. The method of claim 1 , wherein said second silicon nitride layer is in contact with said first silicon nitride layer.

4. The method of claim 1 , wherein said second silicon nitride layer comprises an upper film of stoichiometric silicon nitride.

5. The method of claim 4 , wherein said second silicon nitride layer is in contact with said first silicon nitride layer.

6. The method of claim 1 , wherein said forming said tunnel oxide layer comprises using another atomic layer deposition.

7. The method of claim 1 , wherein said first non-stoichiometric silicon nitride layer and said first silicon nitride layer are part of a non-volatile memory.

8. The method of claim 1 , wherein said using said silicon precursor comprises injecting said silicon precursor for approximately a sixth of a cycle of said first atomic layer deposition.

9. A method comprising:

forming a tunnel oxide layer on a silicon substrate;

depositing via a first atomic layer deposition a first non-stoichiometric silicon nitride layer onto said tunnel oxide layer, said first non-stoichiometric silicon nitride layer comprising a first silicon richness value, said depositing comprises using a silicon precursor, a molecular nitrogen purge, and a nitrogen precursor;

reducing said first silicon richness value by a predefined amount to produce a second silicon richness value;

depositing via a second atomic layer deposition a first silicon nitride layer above said first non-stoichiometric silicon nitride layer, said first silicon nitride layer comprises an upper film of stoichiometric silicon nitride, said first silicon nitride layer comprising said second silicon richness value;

reducing said second silicon richness value by another predefined amount to produce a third silicon richness value; and

depositing via a third atomic layer deposition a second silicon nitride layer above said first silicon nitride layer, said second silicon nitride layer comprises said third silicon richness value.

10. The method of claim 9 , further comprising:

reducing said third silicon richness value by another predefined amount to produce a fourth silicon richness value.

11. The method of claim 9 , wherein said using said molecular nitrogen purge comprises performing said molecular nitrogen purge for approximately a third of a cycle of said first atomic layer deposition.

12. The method of claim 9 , wherein said first non-stoichiometric silicon nitride layer, said first silicon nitride layer, and said second silicon nitride layer are part of an integrated circuit non-volatile memory.

13. A method comprising:

forming a tunnel oxide layer on a substrate;

depositing via a first atomic layer deposition a first non-stoichiometric silicon nitride layer onto said tunnel oxide layer, said first non-stoichiometric silicon nitride layer comprises a first silicon richness value, said depositing comprises using a silicon precursor and a molecular nitrogen purge;

changing said first silicon richness value by a predefined amount to produce a second silicon richness value;

depositing via a second atomic layer deposition a first silicon nitride layer above said first non-stoichiometric silicon nitride layer, said first silicon nitride layer comprises said second silicon richness value;

changing said second silicon richness value by another predefined amount to produce a third Silicon richness value; and

depositing via a third atomic layer deposition a second silicon nitride layer above said first silicon nitride layer, said second silicon nitride layer comprises said third silicon richness value.

14. The method of claim 13 , wherein said first silicon nitride layer is in contact with said first non-stoichiometric silicon nitride layer.

15. The method of claim 13 , wherein said second silicon nitride layer is in contact with said first silicon nitride layer.

16. The method of claim 13 , wherein said second silicon nitride layer comprises an upper film of stoichiometric silicon nitride.

17. The method of claim 16 , wherein said second silicon nitride layer is in contact with said first silicon nitride layer.

18. The method of claim 13 , wherein said forming said tunnel oxide layer comprises using another atomic layer deposition.

19. The method of claim 13 , wherein said first non-stoichiometric silicon nitride layer and said first silicon nitride layer are part of a non-volatile memory.

20. The method of claim 13 , wherein said using said silicon precursor comprises injecting said silicon precursor for approximately a sixth of a cycle of said first atomic layer deposition.

Assignments (8)