IP Library Granted Patent US 8,338,246
Granted Patent B2
US 8,338,246 · App. 12/571,298 · Granted Dec 25, 2012

Method for fabricating a semiconductor device having a device isolation trench

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,338,246
App. No.
12/571,298
Granted
Dec 25, 2012
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes forming a semiconductor substrate to have a SOI structure by an epitaxial process for forming a gate while forming an insulating film pattern in a bottom where a device isolation trench is formed. The method thereby increases the process margin for forming a device isolation film and prevents the punch-through phenomenon to improve electrical characteristics of semiconductor devices and increase product yield.

Claims (16)

1. A method for fabricating a semiconductor device, comprising:

patterning a deposited insulating film on a bottom silicon substrate to form an insulating film pattern that exposes a region of the bottom silicon substrate;

forming an epitaxial layer on the exposed region of the bottom silicon substrate and the insulating film pattern;

partially etching the epitaxial layer to form a device isolation trench and a recess, wherein the device isolation trench defines an active region, and wherein the insulating film pattern is overlapped with both edges of the active region in a length direction and remains to form part of the semiconductor device;

forming an oxide film in the device isolation trench and the recess;

removing the oxide film in the recess; and

forming a gate in the recess.

2. The method according to claim 1 , wherein the act of partially etching the epitaxial layer comprises:

forming a hard mask pattern over the epitaxial layer; and

etching the epitaxial layer using the hard mask pattern as an etching mask.

3. The method according to claim 2 , further comprising:

removing the hard mask pattern and then performing an ion-implanting process on the active region, and wherein the act of forming a gate in the recess includes filling a conductive material over the recess.

4. The method according to claim 1 , wherein the exposed region of the bottom silicon substrate is disposed between separated portions of the insulating film pattern.

5. The method according to claim 4 , wherein:

the epitaxial layer is formed in contact with the bottom silicon substrate between the separated portions of the insulating film pattern; and

the epitaxial layer is formed in contact with exposed sidewalls of each of the separated portions of the insulating film patterns.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE IS HYNIX SEMICONDUCTOR INC. NOT HYNIX-SEMICONDUCTOR INC. THERE IS NO HYPHEN IN THE NAME. PREVIOUSLY RECORDED ON REEL 67328 FRAME 814. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded May 14, 2024
From: HYNIX SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067412/0482 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067369/0832 →
CHANGE OF NAME Recorded May 6, 2024
From: HYNIX-SEMICONDUCTOR INC.
To: SK HYNIX INC.
Reel/Frame 067328/0814 →