Flexible memory controller for autonomous mapping of memory
View Patent ↗A memory controller implements flexible memory mapping for storage of data units in a memory. The memory controller logically partitions the memory into a plurality of blocks or block segments and manages the storage of data units among the plurality of blocks/block segments. The memory controller can operate in one of three modes: a monolithic mode whereby the memory is modeled as a plurality of blocks, whereby each block is treated as a “monolithic” block; a fragmented mode whereby the memory is modeled as a plurality of blocks segments of varying sizes; and a combined mode whereby the memory is initially partitioned into a plurality of equal-sized blocks, and whereby each block can be used as a monolithic block or a fragmented block comprising a plurality of block segments of different sizes, and wherein monolithic blocks can be converted to fragmented blocks and fragmented blocks can be converted back to monolithic blocks.
1. A method for mapping a memory, the method comprising:
logically partitioning, using a hardware controller, a portion of the memory having a size 2^k, k being an integer number greater than one, into a first set of k block segments of different sizes such that a block segment i of the first set of k block segments has a size 2^i for i=0 to k−1, and a first mapping information block containing information identifying locations of the k block segments, the first mapping information block being of a size equal to a smallest block segment;
mapping, via the hardware controller, a first block segment of the first set of k block segments to a first data unit; and
modifying a value stored at the first mapping information block to identify the first block segment as being mapped to a data unit.
2. The method of claim 1 , further comprising:
modifying a global mapping value stored at a local storage component of the hardware controller to indicate the portion of the memory is partitioned into the first set of k block segments; and
modifying a value at a first entry of a table stored at the local storage component to indicate at least one block segment of the portion of the memory is mapped to the first data unit.
3. The method of claim 2 , wherein mapping the first block segment to the first data unit comprises:
identifying the first block segment for mapping to the first data unit based on a size of a first data portion of the first data unit.
4. The method of claim 2 , further comprising:
receiving a first data portion of the first data unit and an identifier associated with the first entry at the hardware controller;
indexing, using the hardware controller, the first entry based on the identifier to access a value at the first entry;
identifying, using the hardware controller, the first block segment as mapped to the first data unit based on the value at the first entry; and
storing the first data portion to the first block segment in response to identifying the first block segment.
5. The method of claim 2 , further comprising:
receiving a request at the hardware controller, the request comprising one of an erase request to erase the first data unit from the memory or a read request to read the first data unit from the memory;
in response to the request:
indexing, using the hardware controller, the first entry based on the identifier to access the value at the first entry; and
identifying, using the hardware controller, the first block segment as storing data of the first data unit based on the value at the first entry; and
in response to the request comprising the erase request, modifying, using the hardware controller, the value at the first entry to indicate the first block segment is not mapped to any data unit.
6. The method of claim 5 , further comprising:
responsive to the request comprising the erase request and responsive to determining that each block segment of the first set is not mapped to a data unit, logically combining each block segment of the first set into a single block segment having a size 2^k using the hardware controller.
7. The method of claim 1 , further comprising:
mapping, via the hardware controller, a second block segment of the first set to the first data unit; and
modifying the value stored at the first mapping information block to identify the second block segment of the first set as mapped to the first data unit.
8. The method of claim 1 , further comprising:
in response to determining a select data portion of the first data unit has a size that is not equal to a size of any unmapped block segments of the first set:
logically partitioning, using the hardware controller, a second block segment of the first set having a size 2^j greater than the size of the select data portion into a second set of j block segments of different sizes such that a block segment i of the second set has a size 2^i for i=0 to j−1, and a second mapping information block containing information identifying locations of the block segments, the second mapping information block being of a size equal to a smallest block segment;
mapping a subset of block segments of the second set to the first data unit using the hardware controller, the subset of block segments of the second set having a collective size equal to the size of the select data portion;
modifying a value stored at the first mapping information block to identify the second block segment of the first set as being mapped to a data unit; and
modifying a value stored at the second mapping information block to identify the subset of block segments of the second set as being mapped to a data unit.
9. The method of claim 8 , further comprising:
in response to erasing the select data portion from the subset of block segments of the second set:
logically combining the second set of block segments back into the second block segment responsive to determining each block segment of the second set is not mapped to a data unit.
10. A memory controller comprising:
a memory interface to couple to a memory;
a data interface to couple to one or more data processing components; and
a hardware controller coupled to the memory interface and the data interface, the hardware controller to logically partition a portion of the memory having a size 2^k, k being an integer number greater than one, into a first set of k block segments of different sizes such that a block segment i of the first set of k block segments has a size 2^i for i=0 to k−1, and a first mapping information block containing information identifying locations of the k block segments, the first mapping information block being of a size equal to a smallest block segment, the hardware controller further to map a first block segment of the first set to a first data unit, and modify a value stored at the first mapping information block to identify the first block segment as being mapped to a data unit.
11. The memory controller of claim 10 , further comprising:
a local storage component to store a global mapping value and a table; and
wherein the hardware controller further is to modify the global mapping value to indicate the portion of the memory is partitioned into the first set and to modify a value at a first entry of the table to indicate at least one block segment of the portion of the memory is mapped to the first data unit.
12. The memory controller of claim 11 , wherein:
the memory controller is to receive an erase request to erase the first data unit from the memory, the erase request comprising an identifier associated with the first entry; and
in response to the erase request, the hardware controller is to index the first entry based on the identifier to access a value at the first entry, identify the first block segment as storing data of the first data unit based on the value at the first entry, and erase the first block segment in response to identifying the first block segment, and wherein the hardware controller further is to modify the value at the first entry to indicate the first block segment is not mapped to any data unit in response to erasing the first block segment.
13. The memory controller of claim 12 , wherein the hardware controller further is to logically combine each block segment of the first set into a single block segment having a size 2^k responsive to determining that each block segment of the first set is not mapped to a data unit.
14. The memory controller of claim 11 , wherein:
the memory controller is to receive a read request to read the first data unit from the memory, the read request comprising an identifier associated with the first entry; and
in response to the read request, the hardware controller is to index the first entry based on the identifier to access the value at the first entry, identify the first block segment as storing data of the first data unit based on the value at the first entry, and read a data portion of the data unit from the first block segment in response to identifying the first block segment.
15. The memory controller of claim 10 , wherein:
the hardware controller further is to logically partition the memory into a plurality of monolithic blocks, each monolithic block having a size 2^k, whereby the portion of the memory comprises a first monolithic block of the memory; and
the hardware controller is to logically partition the first monolithic block into the first set of block segments in response to receiving a data portion of the first data unit that is smaller than the size of the monolithic blocks.
16. The memory controller of claim 15 , wherein, in response to identifying a data portion of a second data unit is smaller than the size of the monolithic blocks, the hardware controller is to logically partition a second monolithic block of the plurality of monolithic blocks into a second set of k block segments of different sizes such that a block segment i of the second set has a size B^i for i=0 to k−1 and a second mapping information block being of a size equal to a smallest block segment, and wherein the hardware controller further is to map a first block segment of the second set to the second data unit and to modify a value stored at the second mapping information block to identify the first block segment of the second set as being mapped to a data unit.
17. The memory controller of claim 16 , wherein:
the hardware controller further is to map a second block segment of the second set to the first data unit in response to identifying the second block segment as available for mapping to a data unit, and to modify the value stored at the second mapping information block to identify the second block segment of the second set as mapped to the first data unit; and
the hardware controller is to identify the second block segment of the second set as available for mapping based on the value stored at the second mapping information block.
18. The memory controller of claim 10 , wherein the hardware controller further is to map a second block segment of the first set to the first data unit and to modify the value stored at the first mapping information block to identify the second block segment as mapped to the first data unit.
19. The memory controller of claim 10 , wherein, in response to identifying a select data portion of the first data unit having a size that is not equal to a size of any unmapped block segments of the first set, the hardware controller is to logically partition a second block segment of the first set having a size 2^j greater than the size of the select data portion into a second set of j block segments of different sizes such that a block segment i of the second set has a size B^i for i=0 to j−1 and a second mapping information block containing information identifying locations of the j block segments, the second mapping information block being of a size equal to a smallest block segment, wherein the hardware controller further is to map a subset of block segments of the second set to the first data unit, the subset of block segments of the second set having a collective size equal to the size of the select data portion, and wherein the hardware controller is to modify a value stored at the first mapping information block to identify the second block segment of the first set as being mapped to a data unit and to modify a value stored at the second mapping information block to identify the subset of block segments of the second set as being mapped to a data unit.
20. The memory controller of claim 19 , wherein, in response to erasing the select data portion from the subset of block segments of the second set, the hardware controller further is to logically combine the second set of block segments back into the second block segment responsive to determining each block segment of the second set is not mapped to a data unit.