Semiconductor wafer having scribe lane alignment marks for reducing crack propagation
View Patent ↗A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material.
1. A semiconductor wafer comprising:
at least a first die;
at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die; and
a first alignment mark group used for aligning the wafer to a tool used for patterning the wafer, the first alignment mark group located entirely within the area between the first die and the second die, wherein the first alignment mark group includes a first plurality of alignment lines and wherein each line of the first plurality of alignment lines is formed using a first plurality of discontinuous segments separated from each other by a first plurality of gaps filled with an insulating material;
a second alignment mark group used for aligning the wafer to a tool used for patterning the wafer, the second alignment mark group located entirely within the area between first die and the second die, wherein the second alignment mark group includes a second plurality of alignment lines, and wherein each line of the second plurality of alignment lines is formed using a second plurality of discontinuous segments separated from each other by a second plurality of gaps filled with an insulating material; and
a reference mark positioned between the first alignment mark group and the second alignment mark group that functions as a nominal alignment center.
2. The semiconductor wafer of claim 1 , wherein the first plurality of discontinuous segments are formed either in a first plurality of metal layers of the wafer or in a first plurality of via layers of the wafer and the second plurality of discontinuous segments are formed either in a second plurality of metal layers of the wafer or in a second plurality of via layers of the wafer.
3. The semiconductor wafer of claim 1 , wherein a length of each of the first plurality of discontinuous segments is at least three times greater than a length of each of the first plurality of gaps filled with the insulating material.
4. The semiconductor wafer of claim 1 further comprising at least a third alignment mark group used for aligning the wafer to a tool used for patterning the wafer, the third alignment mark group located entirely within the area between the first die and the second die, wherein the third alignment mark group includes a third plurality of alignment lines, and wherein each line of the third plurality of alignment lines is formed using a third plurality of discontinuous segments separated from each other by a third plurality of gaps filled with an insulating material.
5. The semiconductor wafer of claim 4 further comprising at least a fourth alignment mark group used for aligning the wafer to the tool used for patterning the wafer, the fourth alignment mark group located entirely within the area between first die and the second die, wherein the fourth alignment mark group includes a fourth plurality of alignment lines, and wherein each line of the fourth plurality of alignment lines is formed using a fourth plurality of discontinuous segments separated from each other by a fourth plurality of gaps filled with an insulating material.
6. The semiconductor wafer of claim 1 , wherein the area between the first die and second die is for cutting in a direction orthogonal to the first plurality of alignment lines.
7. The semiconductor wafer of claim 1 , wherein the first plurality of discontinuous segments are formed using a conductive material comprising at least copper.
8. A semiconductor wafer comprising:
at least a first die;
at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die; and
a first alignment mark for aligning the wafer to a tool used for patterning the wafer, the first alignment mark located entirely within the area between the first die and the second die, wherein the first alignment mark includes a central reference mark and a first alignment line and a second alignment line located on opposite sides of the central reference mark, and wherein the first alignment line is formed using a first plurality of discontinuous segments separated from each other by a first plurality of gaps filled with an insulating material and the second alignment line is formed using a second plurality of discontinuous segments separated from each other by a second plurality of gaps filled with the insulating material, wherein the central reference mark functions as a nominal alignment center.
9. The semiconductor wafer of claim 8 , wherein the first plurality of discontinuous segments are formed either in a first plurality of metal layers of the wafer or in a first plurality of via layers of the wafer and the second plurality of discontinuous segments are either formed in a second plurality of metal layers of the wafer or in a second plurality of via layers of the wafer.
10. The semiconductor wafer of claim 8 , wherein a length of each of the first plurality of discontinuous segments is at least three times greater than a length of each of the first plurality of gaps filled with the insulating material and wherein a length of each of the second plurality of discontinuous segments is at least three times greater than a length of each of the second plurality of gaps filled with the insulating material.
11. The semiconductor wafer of claim 8 , wherein the first plurality of discontinuous segments are formed using a conductive material comprising at least copper.
12. A semiconductor wafer comprising:
at least a first die;
at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die; and
a first alignment mark group used for aligning the wafer to a tool used for patterning the wafer, the first alignment mark group located entirely within the area between the first die and the second die, wherein the first alignment mark group includes: (1) a first plurality of alignment lines formed in a first layer, and wherein each line of the first plurality of alignment lines is formed using a first plurality of discontinuous segments separated from each other by a first plurality of gaps filled with an insulating material, and (2) a second plurality of alignment lines formed in a second layer, wherein the second layer is below the first layer, and wherein each line of the second plurality of alignment lines is formed using a second plurality of discontinuous segments separated from each other by a second plurality of gaps filled with an insulating material;
a second alignment mark group used for aligning the wafer to a tool used for patterning the wafer, the second alignment mark group located entirely within the area between first die and the second die, wherein the second alignment mark group includes (1) a third plurality of alignment lines formed in the first layer, and wherein each line of the third plurality of alignment lines is formed using a third plurality of discontinuous segments separated from each other by a third plurality of gaps filled with an insulating material, and (2) a fourth plurality of alignment lines formed in the second layer, wherein the second layer is below the first layer, and wherein each line of the fourth plurality of alignment lines is formed using a fourth plurality of discontinuous segments separated from each other by a fourth plurality of gaps filled with an insulating material; and
a reference mark positioned between the first alignment mark group and the second alignment mark group that functions as a nominal alignment center.
13. The semiconductor wafer of claim 12 further comprising at least a third alignment mark group used for aligning the wafer to a tool used for patterning the wafer, the third alignment mark group located entirely within the area between first die and the second die, wherein the third alignment mark group includes (1) a fifth plurality of alignment lines formed in the first layer, and wherein each line of the fifth plurality of alignment lines is formed using a fifth plurality of discontinuous segments separated from each other by a fifth plurality of gaps filled with an insulating material, and (2) a sixth plurality of alignment lines formed in the second layer, wherein the second layer is below the first layer, and wherein each line of the sixth plurality of alignment lines is formed using a sixth plurality of discontinuous segments separated from each other by a sixth plurality of gaps filled with an insulating material.
14. The semiconductor wafer of claim 13 further comprising at least a fourth alignment mark group used for aligning the wafer to the tool used for patterning the wafer, the fourth alignment mark group located entirely within the area between first die and the second die, wherein the fourth alignment mark group includes (1) a seventh plurality of alignment lines formed in the first layer, and wherein each line of the seventh plurality of alignment lines is formed using a seventh plurality of discontinuous segments separated from each other by a seventh plurality of gaps filled with an insulating material, and (2) an eighth plurality of alignment lines formed in the second layer, wherein the second layer is below the first layer, and wherein each line of the eighth plurality of alignment lines is formed using an eighth plurality of discontinuous segments separated from each other by an eighth plurality of gaps filled with an insulating material.
15. The semiconductor wafer of claim 12 , wherein the area between the first die and second die is for cutting in a direction orthogonal to the first plurality of alignment lines.
16. The semiconductor wafer of claim 14 , wherein the first plurality of alignment lines, the third plurality of alignment lines, the fifth plurality of alignment lines, and the seventh plurality of alignment lines are formed in the first layer and the second plurality of alignment lines, the fourth plurality of alignment lines, the sixth plurality of alignment lines, and the eighth plurality of alignment lines formed in the second layer are formed such as they do not overlap.
17. The semiconductor wafer of claim 12 , wherein a length of each of the first plurality of discontinuous segments is at least three times greater than a length of each of the first plurality of gaps filled with the insulating material and wherein a length of each of the second plurality of discontinuous segments is at least three times greater than a length of each of the second plurality of gaps filled with the insulating material.
18. The semiconductor wafer of claim 17 , wherein the first plurality of discontinuous segments, the second plurality of discontinuous segments, the third plurality of discontinuous segments, the fourth plurality of discontinuous segments, the fifth plurality of discontinuous segments, the sixth plurality of discontinuous segments, the seventh plurality of discontinuous segments, and the eighth plurality of discontinuous segments are formed using a conductive material comprising at least copper.