Integrated circuit reliability
View Patent ↗A method of manufacturing an integrated circuit having minimized electromigration effect, wherein the integrated circuit comprises one or more interconnect, said the or each interconnect comprising a dielectric layer having an intrinsic parameter at a first defined value, characterized in that said method comprises: identifying one or more characteristics of the or each interconnect; determining a minimal process distance from the or each interconnect for the application of one or more first metal elements; calculating a required correction parameter which can correct the intrinsic parameter at said first defined value; calculating a required number of the first metal elements which have the intrinsic parameter at a second defined value, such that the second defined value provides the required correction parameter for the first defined value; applying a plurality of said first metal elements around the interconnect at said minimum process distance to overcome the problem of electromigration caused by the intrinsic parameter at the first defined value.
1. A method of manufacturing an integrated circuit having reduced electromigration effect, wherein the integrated circuit comprises one or more interconnects, each interconnect of said one or more interconnects comprising a dielectric layer made of a material having a Young's modulus at a first defined value linked to the material of the dielectric layer, characterized in that said method comprises:
identifying one or more characteristics of said each interconnect;
determining, at a computer, a minimum process distance from said each interconnect for the application of one or more first metal dummies;
calculating, at the computer, a required correction parameter which can correct the Young's modulus at said first defined value linked to the material of the dielectric layer;
calculating, at the computer, a required number of the first metal dummies which have a Young's modulus at a second defined value linked to the material of the dummies, such that the second defined value provides the required correction parameter for the first defined value linked to the material of the dielectric layer by using the Blech product; and
determining, at the computer, where to apply a plurality of said first metal dummies around the interconnect at said minimum process distance to provide a corrected Young's modulus at a combined value of the first defined value and the second defined value.
2. The method as claimed in claim 1 , wherein identifying characteristics of the interconnect comprises identifying characteristics in a list which includes the length, the material and the first defined value of the Young's modulus of the dielectric layer of said each interconnect.
3. The method as claimed in claim 2 , wherein the method further comprises calculating, at the computer, a number of second metal dummies having a third defined value linked to the homogeneous density of the integrated circuit of Young's modulus in order to obtain an even metal density of said layer of the integrated circuit.
4. The method as claimed in claim 2 , wherein the method further comprises determining at the computer where to provide a plurality of second metal dummies related to said each interconnect of the integrated circuit, outside the space defined by the plurality of first metal dummies.
5. The method of claim 4 , wherein determining where to provide the plurality of second metal dummies comprises providing copper dummies.
6. The method of claim 2 , wherein determining where to provide the plurality of first metal dummies comprises providing copper dummies.
7. The method as claimed in claim 1 , wherein the method further comprises calculating, at the computer, a number of second metal dummies having a third defined value linked to the homogeneous density of the integrated circuit of Young's modulus in order to obtain an even metal density of said layer of the integrated circuit.
8. The method as claimed in claim 7 , wherein the method further comprises determining, at the computer, where to provide a plurality of second metal dummies related to said each interconnect of the integrated circuit, outside the space defined by the plurality of first metal dummies.
9. The method of claim 8 , wherein determining where to provide the plurality of second metal dummies comprises providing copper dummies.
10. The method of claim 7 , wherein determining where to provide the plurality of first metal dummies comprises providing copper dummies.
11. The method as claimed in claim 1 , wherein the method further comprises determining, at the computer, at the location where to provide a plurality of second metal dummies related to said each interconnect of the integrated circuit, outside the space defined by the plurality of first metal dummies.
12. The method of claim 11 , wherein the plurality of second metal dummies comprise copper.
13. The method of claim 11 , wherein determining where to provide the plurality of first metal dummies comprises providing copper dummies.
14. The method of claim 1 , wherein providing the plurality of first metal dummies comprises providing copper dummies.
15. An integrated circuit comprising:
one or more interconnects, each interconnect of said one or more interconnects comprising a dielectric layer having a Young's modulus at a first defined value linked to the material of the dielectric layer wherein first metal dummies are located at a minimal process distance from an interconnect of said one or more interconnects, said first metal dummies having a second defined value linked to the material of the dummies which provides a required correction parameter for the first defined value in order to overcome an electromigration effect caused by the Young's modulus at the first defined value.
16. The integrated circuit of claim 15 wherein second metal dummies having a third defined value are located outside the space defined by the plurality of first metal dummies.
17. A computer-readable storage medium having a computer-executable program comprising instructions, that when executed by a computer carry out the method comprising:
for an integrated circuit comprising one or more interconnects, each interconnect of said one or more interconnects comprising a dielectric layer made of a material having a Young's modulus at a first defined value linked to the material of the dielectric layer identifying one or more characteristics of said each interconnect;
determining a minimum process distance from said each interconnect for the application of one or more first metal dummies;
calculating a required correction parameter which can correct the Young's modulus 23 at said first defined value linked to the material of the dielectric layer;
calculating a required number of the first metal dummies which have a Young's modulus at a second defined value linked to the material of the dummies, such that the second defined value provides the required correction parameter for the first defined value linked to the material of the dielectric layer by using the Blech product;
applying a plurality of said first metal dummies around said each interconnect at said minimum process distance to provide a corrected Young's modulus at a combined value of the first defined value and the second defined value.