Power lead-on-chip ball grid array package
View Patent ↗A packaging assembly ( 30 ), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die ( 52 ) by using an encapsulated patterned leadframe conductor ( 59 ) that is disposed over the die ( 52 ) and bonded to a plurality of bonding pads ( 45 ) formed in a BGA carrier substrate ( 42 ) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.
1. A method for making a package assembly comprising:
providing a carrier substrate having a plurality of reference voltage terminal package landing pads and a plurality of signal line package landing pads formed on a first surface of the carrier substrate;
attaching an integrated circuit die to the first surface of the carrier substrate where the integrated circuit die comprises an active surface having a plurality of die level reference voltage supply terminals and a plurality of die level signal terminals;
affixing a conductive structure of a first leadframe power conductor to at least two of the reference voltage terminal package landing pads so that the conductive structure of the first leadframe power conductor is electrically connected to the reference voltage terminal package landing pads and disposed over an interior region of the integrated circuit die;
electrically connecting the conductive structure of the first leadframe power conductor to the plurality of die level reference voltage supply terminals in the interior region of the integrated circuit die;
encapsulating the integrated circuit die and first leadframe power conductor to completely enclose the first leadframe power conductor;
wherein electrically connecting the conductive structure of the first leadframe power conductor to the plurality of die level reference voltage supply terminals comprises wirebonding the plurality of die level reference voltage supply terminals to the conductive structure of the first leadframe power conductor with a plurality of wirebond conductors prior to encapsulating the integrated circuit die.
2. The method of claim 1 , where attaching the integrated circuit die to the first surface of the carrier substrate comprises attaching the integrated circuit die so that the active surface of the integrated circuit die faces away from the first surface of the carrier substrate.
3. The method of claim 1 , further comprising wirebonding the plurality of signal line package landing pads to the plurality of die level signal terminals on the integrated circuit die prior to encapsulating the integrated circuit die.
4. The method of claim 1 , further comprising affixing a second leadframe power conductor to at least two different reference voltage terminal package landing pads so that the second leadframe power conductor is electrically connected to the at least two different reference voltage terminal package landing pads and disposed over the interior region of the integrated circuit die.
5. The method of claim 4 , where the conductive structure of the first leadframe power conductor is electrically connected to a first reference voltage and the second leadframe power conductor is electrically connected to a second reference voltage.
6. The method of claim 4 , where affixing the second leadframe power conductor comprises stacking the second leadframe power conductor over the first leadframe power conductor.
7. The method of claim 4 , where affixing the second leadframe power conductor comprises affixing the second leadframe power conductor in an open area defined by the first leadframe power conductor.
8. The method of claim 1 , where electrically connecting the conductive structure of the first leadframe power conductor comprises electrically connecting the first leadframe power conductor to a plurality of die level ground supply terminals in the interior region of the integrated circuit die.
9. The method of claim 1 , where electrically connecting the conductive structure of the first leadframe power conductor comprises electrically connecting the conductive structure of the first leadframe power conductor to a plurality of die level V DD supply terminals in the interior region of the integrated circuit die.
10. The method of claim 1 , where electrically connecting the conductive structure of the first leadframe power conductor comprises electrically connecting the conductive structure of the first leadframe power conductor to a plurality of die level V ss supply terminals in the interior region of the integrated circuit die.
11. A packaging assembly-comprising:
a carrier substrate comprising a first surface and a plurality of conductive bonding pads located at the first surface for supplying a reference voltage;
an integrated circuit comprising an active surface with a plurality of signal bonding pads and a plurality of reference voltage bonding pads distributed across the active surface;
a patterned leadframe conductor disposed over the active surface of the integrated circuit and electrically connected to the plurality of reference voltage bonding pads and the plurality of conductive bonding pads thereby electrically coupling the integrated circuit to the carrier substrate; and
an insulating package body affixed to the carrier substrate so that the patterned leadframe conductor is completely encapsulated in the packaging assembly;
wherein the patterned leadframe conductor includes a conductive structure of a contiguous conductive material disposed over the active surface of the integrated circuit and extending outward from the integrated circuit and downward towards the carrier substrate and electrically connected to a first plurality of conductive bonding pads;
a plurality of wire bonds, each electrically connected and attached to a reference voltage bonding pad of a first plurality of reference voltage bonding pads and to the conductive structure of the patterned leadframe conductor.
12. The packaging assembly of claim 11 , where the patterned leadframe conductor comprises:
a first patterned leadframe conductor disposed over the active surface of the integrated circuit and electrically connected to a first plurality of reference voltage bonding pads and a first plurality of conductive bonding pads, and
a second patterned leadframe conductor disposed over the active surface of the integrated circuit and electrically connected to a second plurality of reference voltage bonding pads and a second plurality of conductive bonding pads.
13. The packaging assembly of claim 12 , where the second patterned leadframe conductor is positioned to overlap at least in part the first patterned leadframe conductor.
14. A packaging assembly-comprising:
a carrier substrate comprising a first surface and a plurality of conductive bonding pads located at the first surface for supplying a reference voltage;
an integrated circuit comprising an active surface with a plurality of signal bonding pads and a plurality of reference voltage bonding pads distributed across the active surface;
a patterned leadframe conductor disposed over the active surface of the integrated circuit and electrically connected to the plurality of reference voltage bonding pads and the plurality of conductive bonding pads thereby electrically coupling the integrated circuit to the carrier substrate; and
an insulating package body affixed to the carrier substrate so that the patterned leadframe conductor is completely encapsulated in the packaging assembly;
where the patterned leadframe conductor comprises:
a first patterned leadframe conductor disposed over the active surface of the integrated circuit and electrically connected to a first plurality of reference voltage bonding pads and a first plurality of conductive bonding pads, and
a second patterned leadframe conductor disposed over the active surface of the integrated circuit and electrically connected to a second plurality of reference voltage bonding pads and a second plurality of conductive bonding pads;
where the second patterned leadframe conductor is positioned adjacent to the first patterned leadframe conductor so that there is no overlap between the first and second patterned leadframe conductors.
15. A packaging assembly-comprising:
a carrier substrate comprising a first surface and a plurality of conductive bonding pads located at the first surface for supplying a reference voltage;
an integrated circuit comprising an active surface with a plurality of signal bonding pads and a plurality of reference voltage bonding pads distributed across the active surface;
a patterned leadframe conductor disposed over the active surface of the integrated circuit and electrically connected to the plurality of reference voltage bonding pads and the plurality of conductive bonding pads thereby electrically coupling the integrated circuit to the carrier substrate; and
an insulating package body affixed to the carrier substrate so that the patterned leadframe conductor is completely encapsulated in the packaging assembly;
where the patterned leadframe conductor comprises a two-layer composite structure having a dielectric layer and two conductive layers formed together so as to position the dielectric layer between the two conductive layers, whereby each of the conductive layers is a patterned leadframe conductor.
16. The packaging assembly of claim 11 , where the active surface of the integrated circuit is opposite the first surface of the carrier substrate.
17. The packaging assembly of claim 11 , further comprising a plurality of wirebond connectors for electrically connecting a plurality of signal line package landing pads formed on the first surface of the carrier substrate to the plurality of signal bonding pads formed on the active surface of the integrated circuit.