Process for the preparation of silicon wafer with reduced slip and warpage
View Patent ↗Silicon wafers wherein slip dislocations and warpages during device production are suppressed, contain BMDs with an octahedral shape, and of BMDs at a depth greater than 50 μm from the surface of the wafer, the density of BMDs with diagonal size of 10 nm to 50 nm is ≧1×10 12 /cm 3 , and the density of BSFs is ≦1×10 8 /cm 3 . The present silicon wafers preferably have an interstitial oxygen concentration of 4×10 17 atoms/cm 3 to 6×10 17 atoms/cm 3 , and a density of BMDs with diagonal size of ≧200 nm of not more than 1×10 7 /cm 3 .
1. A process for producing a silicon wafer having no epitaxial layer deposited thereon, wherein a wafer is subjected to a heat treatment comprising:
A: a low temperature heat treatment step wherein the wafer is heat treated at a temperature of from 700° C. to 800° C. for 30 minutes to 5 hours;
B: a temperature increasing step following the low temperature heat treatment step, wherein the wafer is heated up to a temperature of from 900° C. to 1,000° C. at a rate of temperature increase of 0.5° C./minute to 2° C./minute; and
C: a temperature decreasing and unloading step following the temperature increasing step, wherein a temperature in a furnace is decreased at a rate of 1° C./minute to 10° C./minute, and when the temperature of the wafer becomes from 600° C. to 800° C., the wafer is unloaded from the furnace and cooled to room temperature; and
D: a high temperature heat treatment step following the temperature decreasing and unloading step, wherein the temperature in the furnace is at a wafer insertion temperature of from 600° C. to 800° C., the wafer is inserted therein, and the temperature of the wafer is increased at a rate of 5° C./minute to 10° C./minute in the range from the wafer insertion temperature to 1,100° C. and increased at a rate of 1° C./minute to 2° C./minute in the range from 1,100° C. to 1,250° C., and the substrate is maintained at a temperature in the range of 1100° C. to 1250° C. such that the diffusion length of interstitial oxygen is not less than 20 μm,
wherein the silicon wafer contains BMDs of an octahedral shape, and BMDs present at a depth greater than 50 μm from the surface of the silicon wafer having diagonal sizes of 10 nm to 50 nm are present at a density of ≧1×10 12 /cm 3 , and the density of BSFs having sizes of ≧1 μm is <1×10 8 /cm 3 .
2. The process of claim 1 , wherein the interstitial nitrogen concentration in the substrate is 5×10 14 atoms/cm 3 to 1×10 16 atoms/cm 3 .
3. The process of claim 1 , wherein the interstitial carbon concentration in the substrate is 2×10 16 atoms/cm 3 to 2×10 17 atoms/cm 3 .
4. The process of claim 2 , wherein the interstitial carbon concentration in the substrate is 2×10 16 atoms/cm 3 to 2×10 17 atoms/cm 3 .
5. The process of claim 1 , wherein an interstitial oxygen concentration is ≧4×10 17 atoms/cm 3 and ≦6×10 17 atoms/cm 3 , and an interstitial carbon concentration is ≧1×10 16 atoms/cm 3 .
6. The process of claim 1 , wherein the density of BMDs having diagonal sizes of ≧200 nm is ≦1×10 7 /cm 3 .
7. The process of claim 1 , wherein a surface of the silicon wafer has a denuded zone.
8. The process of claim 1 , further comprising depositing an epitaxial layer on the silicon wafer after step (D).