Stacked integrated circuit packages that include monolithic conductive vias
Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.
1. A microelectronic package, comprising:
a plurality of integrated circuits that are stacked upon one another, a respective integrated circuit including a semiconductor layer having microelectronic devices therein and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices; and
a monolithic conductive via that extends through the plurality of integrated circuits including through the semiconductor layers and through the wiring layers thereof, the monolithic conductive via selectively electrically contacting the wiring,
wherein the semiconductor layers include recessed sidewalls relative to the wiring layers, the microelectronic package further comprising an insulating layer between the recessed sidewalls and the monolithic conductive via.
2. A microelectronic package according to claim 1 wherein the plurality of integrated circuits are directly attached to one another without an intervening glue layer.
3. A microelectronic package according to claim 1 wherein the plurality of integrated circuits comprise a plurality of integrated circuit wafers that are stacked upon one another.
4. A microelectronic package according to claim 1 wherein the wiring includes input/output pads and wherein the monolithic conductive via selectively electrically contacts the input/output pads.
5. A microelectronic package according to claim 1 wherein the plurality of integrated circuits comprise a memory integrated circuit, a memory controller integrated circuit, a processor integrated circuit and/or an input/output controller integrated circuit.
6. A microelectronic package, comprising:
a plurality of integrated circuits that are stacked upon one another, a respective integrated circuit including a semiconductor layer having microelectronic devices therein and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices; and
a monolithic conductive via that extends through the plurality of integrated circuits including through the semiconductor layers and through the wiring layers thereof, the monolithic conductive via selectively electrically contacting the wiring,
wherein the plurality of integrated circuits comprises a first and a second integrated circuit that are stacked upon one another such that the wiring layer of the first integrated circuit is adjacent the semiconductor layer of the second integrated circuit;
wherein a sidewall of the semiconductor layer of second integrated circuit is recessed relative to a sidewall of the wiring layer of the first integrated circuit so as to expose a portion of the wiring of the first integrated circuit; and
wherein the monolithic conductive via is a stepped monolithic conductive via that electrically contacts the portion of the wiring of the first integrated circuit.
7. A microelectronic package according to claim 6 further comprising an insulating layer between the sidewalls of the first and second integrated circuits and the monolithic conductive via.
8. A microelectronic package according to claim 6 wherein the plurality of integrated circuits comprise a plurality of integrated circuit wafers that are stacked upon one another.
9. A microelectronic package, comprising:
a plurality of integrated circuits that are stacked upon one another, a respective integrated circuit including a semiconductor layer having microelectronic devices therein and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices; and
a monolithic conductive via that extends through the plurality of integrated circuits including through the semiconductor layers and through the wiring layers thereof, the monolithic conductive via selectively electrically contacting the wiring,
wherein the plurality of integrated circuits are directly attached to one another by oxygen bonds.
10. A microelectronic package according to claim 9 wherein the plurality of integrated circuits comprise a plurality of integrated circuit wafers that are stacked upon one another.