Threshold voltage techniques for detecting an imminent read failure in a memory array
View Patent ↗A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.
1. A method of detecting an imminent read failure in a memory array, comprising:
detecting a correctable error correcting code (ECC) read for a memory array during an initial array integrity check at a normal read verify voltage level;
in response to detecting the correctable ECC read determining whether the memory array exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level, wherein the margin read verify voltage level is different from the normal read verify voltage level; and
providing an indication of an imminent read failure for the memory array in response to the memory array exhibiting the uncorrectable ECC read during the subsequent array integrity check, wherein the imminent read failure indicates a future read failure that will occur at the normal read verify voltage level that is not ECC correctable.
2. The method of claim 1 , wherein the margin read verify voltage level is greater than the normal read verify voltage level.
3. The method of claim 1 , wherein the margin read verify voltage level is less than the normal read verify voltage level.
4. The method of claim 1 , further comprising:
performing the initial array integrity check on the memory array at the normal read verify voltage level.
5. The method of claim 4 , further comprising:
performing the subsequent array integrity check on the memory array at the margin read verify voltage level.
6. The method of claim 1 , wherein the memory array is a non-volatile memory array.
7. A method of detecting an imminent read failure in a memory array, comprising:
performing an initial array integrity check on a memory array at a normal read verify voltage level;
determining whether the initial array integrity check on the memory array passed at the normal read verify voltage level without using error correcting code (ECC) correction;
determining, when the array integrity check on the memory array did not pass at the normal read verify voltage level without using the ECC correction, whether the memory array is ECC correctable;
performing, when the memory array is ECC correctable but did not pass at the normal read verify voltage level without using the ECC correction, a subsequent array integrity check of the memory array at a margin read verify voltage level, wherein the normal read verify voltage is different that the margin read verify voltage level; and
indicating an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check, wherein the imminent read failure indicates a future read failure that will occur at the normal read verify voltage level that is not ECC correctable.
8. The method of claim 7 , wherein the margin read verify voltage level is above the normal read verify voltage level.
9. The method of claim 7 , wherein the margin read verify voltage level is below the normal read verify voltage level.
10. The method of claim 7 , further comprising:
indicating a pass status when the memory array passes the initial array integrity check without ECC correction.
11. The method of claim 7 , further comprising:
indicating a pass status when the memory array does not exhibit any uncorrectable reads during the subsequent array integrity check.
12. The method of claim 7 , further comprising:
indicating a fail status when the memory array is not ECC correctable.
13. The method of claim 7 , further comprising:
indicating a fail status when the memory array exhibits any uncorrectable ECC reads during the subsequent array integrity check.
14. The method of claim 7 , wherein the memory array is a non-volatile memory array.
15. A memory system, comprising:
a non-volatile memory array; and
a circuit coupled to the non-volatile memory array, wherein the circuit is configured to:
perform an initial array integrity check on the non-volatile memory array at a normal read verify voltage level;
determine whether the initial array integrity check on the non-volatile memory array passed at the normal read verify voltage level without using error correcting code (ECC) correction;
determine, when the array integrity check on the non-volatile memory array did not pass at the normal read verify voltage level without using the ECC correction, whether the non-volatile memory array is ECC correctable;
perform, when the non-volatile memory array is ECC correctable but did not pass at the normal read verify voltage level without using the ECC correction, a subsequent array integrity check of the non-volatile memory array at a margin read verify voltage level, wherein the normal read verify voltage level is different that the margin read verify voltage level; and
indicate an imminent read failure for the non-volatile memory array when the non-volatile memory array exhibits an uncorrectable ECC read during the subsequent array integrity check, wherein the imminent read failure indicates a future read failure that will occur at the normal read verify voltage level that is not ECC correctable.
16. The memory system of claim 15 , wherein the margin read verify voltage level is above the normal read verify voltage level.
17. The memory system of claim 15 , wherein the margin read verify voltage level is below the normal read verify voltage level.
18. The memory system of claim 15 , wherein the circuit is further configured to:
indicate a pass status when the non-volatile memory array passes the initial array integrity check without ECC correction.
19. The memory system of claim 15 , wherein the circuit is further configured to:
indicate a pass status when the non-volatile memory array does not exhibit any uncorrectable reads during the subsequent array integrity check.
20. The memory system of claim 15 , wherein the circuit is further configured to:
indicate a fail status when the non-volatile memory array is not ECC correctable; and
indicate a fail status when the non-volatile memory array exhibits any uncorrectable reads during the subsequent array integrity check.
21. A method of detecting an imminent read failure in a memory array, comprising:
determining whether a memory array that exhibits a correctable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level also exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level, wherein the margin read verify voltage level is different from the normal read verify voltage level; and
providing an indication of an imminent read failure for the memory array in response to the memory array exhibiting the uncorrectable ECC read during the array integrity check at the margin read verify voltage level, wherein the imminent read failure indicates a future read failure that will occur at the normal read verify voltage level that is not ECC correctable.