Time-based techniques for detecting an imminent read failure in a memory array
View Patent ↗A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount.
1. A method of detecting an imminent read failure in a memory array, comprising:
determining a first incident count for the memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check, wherein the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails;
determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks, wherein the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks; and
providing an indication of an imminent read failure for the memory array when the current count exceeds the first incident count by a predetermined amount.
2. The method of claim 1 , further comprising:
storing the first incident count in a storage location.
3. The method of claim 1 , further comprising:
indicating a pass status when the memory array passes the array integrity check without ECC correction.
4. The method of claim 1 , further comprising:
indicating a pass status when the current count does not exceed the first incident count by the predetermined value.
5. The method of claim 1 , further comprising:
performing the array integrity check on the memory array at a normal read verify voltage level.
6. The method of claim 1 , wherein the memory array is a non-volatile memory array.
7. A method of detecting an imminent read failure in a memory array, comprising:
determining whether an array integrity check on the memory array passed without using error correcting code (ECC) correction;
determining, when the array integrity check on the memory array did not pass without using the ECC correction, whether the memory array is ECC correctable;
determining, when the memory array is ECC correctable, a first incident count for the memory array, wherein the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails;
determining, while the memory array is ECC correctable, a current count for the memory array during subsequent array integrity checks, wherein the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks; and
providing an indication of an imminent read failure for the memory array when the current count exceeds the first incident count by a predetermined amount.
8. The method of claim 7 , further comprising:
storing the first incident count in a non-volatile storage location.
9. The method of claim 7 , further comprising:
indicating a pass status when the memory array passes the array integrity check without ECC correction.
10. The method of claim 7 , further comprising:
indicating a pass status when the current count does not exceed the first incident count by the predetermined value.
11. The method of claim 7 , further comprising:
performing the array integrity check on the memory array at a normal read verify voltage level.
12. The method of claim 11 , further comprising:
indicating a pass status when the memory array passes the array integrity check without ECC correction.
13. The method of claim 7 , further comprising:
indicating a fail status when the memory array is not ECC correctable.
14. The method of claim 7 , wherein the memory array is a non-volatile memory array.
15. A memory system, comprising:
a non-volatile memory array; and
a circuit coupled to the non-volatile memory array, wherein the circuit is configured to:
determine whether an array integrity check on the memory array passed without using error correcting code (ECC) correction;
determine, when the array integrity check on the memory array did not pass without using the ECC correction, whether the memory array is ECC correctable;
determine, when the memory array is ECC correctable, a first incident count for the memory array, wherein the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails;
determine, while the memory array is ECC correctable, a current count for the memory array during subsequent array integrity checks, wherein the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks; and
provide an indication of an imminent read failure for the memory array when the current count exceeds the first incident count by a predetermined amount.
16. The memory system of claim 15 , wherein the circuit is further configured to:
store the first incident count in a non-volatile storage location.
17. The memory system of claim 15 , wherein the circuit is further configured to:
indicate a pass status when the memory array passes the array integrity check without ECC correction.
18. The memory system of claim 15 , wherein the circuit is further configured to:
indicate a fail status when the memory array is not ECC correctable.
19. The memory system of claim 15 , wherein the circuit is further configured to:
indicate a pass status when the current count does not exceed the first incident count by the predetermined value.
20. The memory system of claim 15 , wherein the circuit is further configured to:
perform the array integrity check on the memory array at a normal read verify voltage level.