Non-volatile memory controller device and method therefor
View Patent ↗A method of storing information at a non-volatile memory includes storing a status bit prior to storing data at the memory. A second status bit is stored after storing of the data. Because the storage of data is interleaved with the storage of the status bits, a brownout or other corrupting event during storage of the data will likely result in a failure to store the second status bit. Therefore, the first and second status bits can be compared to determine if the data was properly stored at the non-volatile memory.
1. A method comprising:
receiving a first memory write request to write first data to a volatile memory location;
in response to receiving the first memory write request:
storing a first status bit at a first record of a non-volatile memory at a first time;
storing the first data at the first record of the non-volatile memory at a second time, the second time after the first time; and
storing a second status bit at the first record of a non-volatile memory at a third time, the third time after the second time.
2. The method of claim 1 , further comprising:
in response to a read request, reading the contents of the first record and determining if the first data at the first record corresponds to data stored at the volatile memory location based on a received value of the first status bit and a received value of the second status bit.
3. The method of claim 2 , wherein reading the contents of the first record further comprises reading the contents of the first record and determining the first record does not correspond to data stored at the volatile memory location in response to determining the received value of the first status bit is different than the received value of the second status bit.
4. The method of claim 1 wherein communicating a request to store the first data at the first record further comprises communicating the request to store the first data at a first data portion of a plurality of data portions of the first record.
5. The method of claim 1 wherein the first memory write request further comprises a request to store the first data at a first address of the volatile memory and further comprising storing the first address at the first record.
6. The method of claim 1 , further comprising:
storing the first data at a first portion of the first record;
receiving a second memory write request to write second data to the volatile memory location, the second request after the first;
in response to receiving the second memory write request, determining if a second portion of the first record is available to store the second data.
7. The method of claim 6 , further comprising:
in response to determining the second portion of the first record is available to store the second data:
storing a third status bit at the first record of a non-volatile memory at a fourth time;
storing the second data at the first record at a fifth time, the fifth time after the fourth time; and
storing a fourth status bit at the first record of a non-volatile memory at a sixth time, the sixth time after the fifth time.
8. The method of claim 7 , further comprising:
receiving a read request associated with the first record after receiving the second memory write request; and
determining if data stored at the first record corresponds to data stored at the volatile memory location based on the first status bit and the second status bit.
9. The method of claim 8 , further comprising determining if data stored at the first record corresponds to data stored at the volatile memory location based on the third status bit and the fourth status bit.
10. The method of claim 9 , wherein determining if data stored at the first record corresponds to data stored at the volatile memory location comprises determining that data stored at the second portion does not correspond to data stored at the volatile memory location in response to determining that a value of the third status bit is different than a value of the fourth status bit.
11. The method of claim 1 , further comprising:
in response to receiving a request to erase the first record, storing a third status bit at the record.
12. A method comprising:
receiving a first memory write request at a volatile memory comprising first data;
in response to receiving the first memory write request:
storing a first status bit at a first record of a non-volatile memory at a first time;
storing the first data at the first record of the non-volatile memory at a second time, the second time after the first time;
storing a second status bit at the first record of the non-volatile memory at a third time, the third time after the second time; and
in response to a read request, reading contents of the first record, wherein reading comprises determining validity of data stored at the first record based on a received value of the first status bit and a received value of the second status bit.
13. The method of claim 12 further comprising:
receiving a second memory write request at the volatile memory comprising second data;
in response to receiving the second memory write request:
storing a third status bit at the first record of a non-volatile memory at a fourth time;
storing the second data at the first record of the non-volatile memory at a fifth time, the fifth time after the fourth time; and
storing a fourth status bit at the first record of the non-volatile memory at a sixth time, the sixth time after the second time.
14. The method of claim 12 , wherein determining the validity of data comprises determining data is invalid in response to determining the received value of the first status bit is different from the received value of the second status bit.
15. The method of claim 12 , further comprising storing the first data at the volatile memory in response to the first memory write request.
16. A device comprising:
a volatile memory comprising a first memory location;
a non-volatile memory including a first record operable to receive information, the record including a first location, a second location, and a third location;
a control module coupled to the non-volatile memory and the volatile memory;
in response to a write request, the control module operable to store a first status bit at the first location at a first time, store first data at the third location at a second time, the second time after the first time; and store a second status bit at the second location at a third time, the third time after the second time.
17. The device of claim 16 , wherein the control module is further operable to determine validity of data stored at the first record based on a value of the first status bit and a value of the second status bit in response to a read request.
18. The device of claim 17 , wherein the control module is configured to indicate a storage error to a processor device in response to determining the data stored at the first record is invalid.
19. The device of claim 17 , wherein the control module is operable to determine the data stored at the first record is invalid in response to determining the value of the first status bit is different from the value of the second status bit.
20. The device of claim 16 wherein the control module is further operable to store the first data information at the volatile memory in response to the first write request.