Simulation method for transistor unsuitable for existing model
View Patent ↗A simulation method includes determining a relationship between stress time and a degradation rate of drain current on a basis of a table in which data of a lifetime of a transistor, or the degradation rate of the transistor, is written, and calculating an amount of change in drain current accordance with the degradation rate, using a table in which information indicating a change in the drain current, being dependent on voltage, is written, based on actually measured data of drain current of the transistor after degradation, drain current in an initial state of a particular transistor model, and the relationship between stress time and the degradation rate of drain current.
1. A simulation method comprising:
determining a relationship between stress time and a degradation rate of drain current on a basis of a first table in which data of a lifetime of an evaluation target transistor, at a reference degradation rate, said lifetime being dependent on voltage, is written for three kinds of voltages, that is, gate voltage, drain voltage and back bias voltage, or on a basis of a second table in which data of said degradation rate of said drain current of said evaluation target transistor, during a reference time, said degradation rate of said drain current being dependent on voltage, is written for said three kinds of voltages; and
calculating an amount of change in drain current in accordance with said degradation rate of said drain current, using a third table in which information indicating a change in said drain current, said information being dependent on voltage, is written for said three kinds of voltages, said third table being based on actually measured data, at said reference degradation, of drain current of said evaluation target transistor after degradation according to said stress time, drain current in an initial state of a particular transistor model and said relationship between said stress time and said degradation rate of said drain current.
2. The simulation method according to claim 1 , further comprising:
generating a fifth table in which data of said lifetime that is dependent on said drain voltage at said reference degradation rate is written, from a fourth table in which data of said lifetime that is dependent on said gate voltage at said reference degradation rate is written.
3. The simulation method according to claim 2 , wherein said fifth table is generated by applying a drain voltage ratio corresponding to a range of said drain voltage in said fifth table to values obtained by correcting said gate voltage in said fourth table according to threshold voltage and multiplying said lifetime at a predetermined degradation rate in said fourth table by predetermined magnification.
4. An information processing apparatus comprising:
a storage section storing a program for a particular transistor model; and
a control section determining a relationship between stress time and a degradation rate of drain current on a basis of a first table in which data of a lifetime of an evaluation target transistor, at a reference degradation rate, said lifetime being dependent on voltage, is written for three kinds of voltages, that is, gate voltage, drain voltage and back bias voltage, or on a basis of a second table in which data of said degradation rate of said drain current of said evaluation target transistor, during a reference time, said degradation rate of said drain current being dependent on voltage, is written for said three kinds of voltages, and calculating an amount of change in drain current in accordance with said degradation rate of said drain current, using a third table in which information indicating a change in said drain current, said information being dependent on voltage, is written for said three kinds of voltages, said third table being based on actually measured data, at said reference degradation, of drain current of said evaluation target transistor after degradation according to said stress time, drain current in an initial state of a particular transistor model and said relationship between said stress time and said degradation rate of said drain current.
5. The information processing apparatus according to claim 4 , wherein, when a fourth table in which data of said lifetime that is dependent on said gate voltage at said reference degradation rate is written, is inputted, said control section generates a fifth table in which data of said lifetime that is dependent on said drain voltage at said reference degradation rate is written, from said fourth table.
6. The information processing apparatus according to claim 5 , wherein said control section generates said fifth table by applying a drain voltage ratio corresponding to a range of said drain voltage in said fifth table to values obtained by correcting said gate voltage in said fourth table according to threshold voltage and multiplying said lifetime at a predetermined degradation rate in said fourth table by predetermined magnification.
7. A storage medium in which a program for causing a computer to execute degradation phenomenon simulation of a transistor is computer-readably recorded, the program being implemented to causing the computer to execute processing of:
determining a relationship between stress time and a degradation rate of drain current on a basis of a first table in which data of a lifetime of an evaluation target transistor, at a reference degradation rate, said lifetime being dependent on voltage, is written for three kinds of voltages, that is, gate voltage, drain voltage and back bias voltage, or on a basis of a second table in which data of said degradation rate of said drain current of said evaluation target transistor, during a reference time, said degradation rate of said drain current being dependent on voltage, is written for said three kinds of voltages; and
calculating an amount of change in drain current in accordance with said degradation rate of said drain current, using a third table in which information indicating a change in said drain current, said information being dependent on voltage, is written for said three kinds of voltages, said third table being based on actually measured data, at said reference degradation, of drain current of said evaluation target transistor after degradation according to said stress time, drain current in an initial state of a particular transistor model and said relationship between said stress time and said degradation rate of said drain current.
8. The storage medium according to claim 7 , wherein a program is recorded which includes processing of, when a fourth table in which data of said lifetime that is dependent on said gate voltage at said reference degradation rate is written, is inputted, generating a fifth table in which data of said lifetime that is dependent on said drain voltage at said reference degradation rate is written, from said fourth table.
9. The storage medium according to claim 8 , wherein a program is recorded which includes processing of generating said fifth table by applying a drain voltage ratio corresponding to a range of said drain voltage in said fifth table to values obtained by correcting said gate voltage in said fourth table according to threshold voltage and multiplying said lifetime at a predetermined degradation rate in said fourth table by predetermined magnification.