Semiconductor device package
View Patent ↗A method for forming a semiconductor device package includes providing a lead frame array having a plurality of leads. Each of the plurality of leads includes an opening extending through the lead from a first surface of the lead to a second surface of the lead, opposite the first surface, and each of the openings is at least partially filled with a solder wettable material. A plurality of semiconductor devices are attached to the lead frame array. The plurality of semiconductor devices are encapsulated, and, after encapsulating, the plurality of semiconductor devices are separated along separation lines which intersect the openings.
1. A method for forming a semiconductor device package, the method comprising:
providing a lead frame array having a plurality of leads, wherein each of the plurality of leads includes an opening extending through the lead from a first surface of the lead to a second surface of the lead, opposite the first surface, and wherein each of the openings is at least partially filled with a solder wettable material;
attaching a plurality of semiconductor devices to the lead frame array;
encapsulating the plurality of semiconductor devices and at least a portion of the lead frame array, wherein the opening of each of the plurality of leads is blocked with the solder wettable material during the encapsulating; and
after the encapsulating, separating the plurality of semiconductor devices along separation lines which intersect the openings.
2. The method of claim 1 , wherein the providing the lead frame array is further characterized by the lead frame array being plated prior to the openings being at least partially filled with the solder wettable material.
3. The method of claim 1 , wherein the providing the lead frame array is further characterized by the lead frame array being plated after the openings are at least partially filled with the solder wettable material.
4. The method of claim 1 , wherein the encapsulating the plurality of semiconductor devices comprises encapsulating the plurality of devices with a continuous encapsulant that covers all of the plurality of devices.
5. The method of claim 1 , wherein the encapsulating the plurality of semiconductor devices comprises encapsulating the plurality of devices with a discontinuous encapsulant.
6. The method of claim 1 , wherein the attaching the plurality of semiconductor devices comprises electrically coupling the plurality of semiconductor devices and corresponding leads of the lead frame array.
7. The method of claim 1 , wherein the providing the lead frame array is further characterized in that, for each of the openings, the solder wettable material that at least partially fills the opening, blocks the opening.
8. The method of claim 1 , wherein the providing the lead frame array is further characterized in that each of the openings is completely surrounded by lead frame material.
9. A method for forming a semiconductor device package, the method comprising:
providing a lead frame array having a plurality of leads, wherein each of the plurality of leads includes an opening extending through the lead from a first surface of the lead to a second surface of the lead, opposite the first surface;
at least partially filling each of the openings with a solder wettable material, wherein the at least partially filling each of the openings blocks each of the openings with the solder wettable material;
attaching a plurality of semiconductor devices to the lead frame array, wherein each semiconductor device is attached to a corresponding die flag of the lead frame array;
plating the lead frame array;
encapsulating the plurality of semiconductor devices wherein the opening of each of the plurality of leads is blocked with the solder wettable material during the encapsulating; and
after the encapsulating, separating the plurality of semiconductor devices along separation lines which intersect the openings.
10. The method of claim 9 , wherein the plating is performed prior to the at least partially filling each of the openings with the solder wettable material.
11. The method of claim 9 , wherein the plating is performed after the at least partially filling each of the openings with the solder wettable material and prior to the attaching the plurality of semiconductor devices.
12. The method of claim 9 , wherein the plating is performed after the encapsulating.
13. The method of claim 9 , wherein the encapsulating the plurality of semiconductor devices comprises encapsulating the plurality of devices with a continuous encapsulant that covers all of the plurality of devices.
14. The method of claim 9 , wherein the attaching the plurality of semiconductor devices comprises forming wire bond connections between the plurality of semiconductor devices and corresponding leads of the lead frame array.
15. A semiconductor device package, comprising:
a semiconductor die;
a lead electrically coupled to the semiconductor die; and
an encapsulant over the semiconductor die and the lead, wherein the lead has a first surface exposed on a major surface of the encapsulant and a second surface exposed on a side surface of the encapsulant, the lead including a third surface that is an opposite surface to the first surface, wherein the second surface is flush with at least a portion of the side surface, wherein the at least a portion of the side surface is perpendicular to the major surface, wherein the lead comprises an opening from the first surface to the third surface of the lead that opens towards the second surface of the lead and the opening includes solder, wherein the solder has a surface flush with the second surface of the lead across the second surface of the lead in a direction that is parallel to both the first surface and the second surface.
16. The semiconductor device package of claim 15 , wherein only the first surface and the second surface of the lead are exposed.
17. The semiconductor device package of claim 15 , wherein the lead further comprises a plated conductive layer.
18. The semiconductor device package of claim 15 , further comprising a die flag, wherein the semiconductor die is attached to a first major surface of the die flag and the encapsulant exposes a second major surface of the die flag, the second major surface of the die flag opposite the first major surface of the die flag.
19. The semiconductor device package of claim 15 , wherein the opening opens out towards the second surface and the first surface of the lead.
20. The semiconductor device package of claim 15 , wherein the first surface of the lead is flush with the major surface of the encapsulant.