Semiconductor device with high K dielectric control terminal spacer structure
View Patent ↗A semiconductor device including a control terminal sidewall spacer structure made of a high-K dielectric material. The semiconductor device includes a control terminal where the spacer structure is a sidewall spacer structure for the control terminal. The semiconductor device includes current terminal regions located in a substrate. In some examples, the spacer structure has a height that is less than the height of the control terminal. In some examples, the spacer structure includes portions located over the regions of the substrate between the first current terminal region and the second current terminal region.
1. A method of forming a semiconductor device with a control terminal, a first current terminal region, and a second current terminal region, the method comprising:
forming a control terminal structure of the control terminal over a substrate, the substrate including semiconductor material;
forming a layer of high-K dielectric material over the substrate and over the control terminal structure;
forming a control terminal sidewall spacer structure of high-K dielectric material for the control terminal structure from the layer of high-K dielectric material, wherein the forming includes etching the layer of high-K dielectric material, wherein the control terminal sidewall spacer structure has a top side that is located closer to the substrate than a mid-plane of the control terminal structure;
forming the first current terminal region and the second current terminal region, wherein the first current terminal region and the second current terminal region each include a portion located in the substrate;
forming a second control terminal sidewall spacer structure for the control terminal after the etching the layer, wherein the forming the second control terminal sidewall spacer structure includes forming a layer of lower-K dielectric material over the substrate including over the control terminal structure and over the control terminal sidewall spacer structure and etching the layer of lower K dielectric material, wherein the second control terminal sidewall spacer structure has a top surface that is farther from the substrate than the mid-plane;
wherein the forming the first current terminal region and the second current terminal region includes:
implanting a first dosage of conductivity dopants in the substrate before the forming the second control terminal sidewall spacer structure;
implanting a second dosage of conductivity dopants in the substrate, wherein the implanting the second dosage occurs after the forming the second control terminal sidewall spacer structure, wherein the second dosage is greater than the first dosage.
2. The method of claim 1 wherein a first region of the substrate includes semiconductor material and is located between the first current terminal region and the second current terminal region, a first portion of the first region is located under the control terminal structure, a second portion of the first region is laterally between the first current terminal region and the first portion of the first region and is located under the control terminal sidewall spacer structure, the second portion is not located under the control terminal structure.
3. The method of claim 2 wherein the first region includes a third portion that is located under the control terminal sidewall spacer structure and is located laterally between the first portion and the second current terminal region, the third portion is not located under the control terminal structure.
4. The method of claim 1 wherein the first current terminal region includes a portion located under the control terminal sidewall spacer structure and the second current terminal region includes a portion located under the control terminal sidewall spacer structure.
5. The method of claim 1 wherein the second control terminal sidewall spacer structure includes a nitride.
6. The method of claim 1 wherein the high-K dielectric material has a dielectric constant of 10.0 or greater and the lower K dielectric material has a dielectric constant of 8.0 or less.
7. The method of claim 1 , the control terminal sidewall spacer structure of the high-K dielectric material has a top surface that is located 200 Angstroms or less from the substrate.
8. The method of claim 1 wherein the high-K dielectric material includes hafnium oxide.
9. The method of claim 1 wherein the semiconductor device is characterized as a transistor with an effective channel length greater than a gate length of the transistor.