IP Library Granted Patent US 8,330,502
Granted Patent B2
US 8,330,502 · App. 12/625,982 · Granted Dec 11, 2012

Systems and methods for detecting interference in an integrated circuit

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Quick Facts
Patent No.
US 8,330,502
App. No.
12/625,982
Granted
Dec 11, 2012
Kind
B2
Abstract

Apparatus, systems and methods are provided for protecting a processing system from electromagnetic interference. An integrated circuit comprises a sensing arrangement configured to sense an interference signal and an interference detection module coupled to the sensing arrangement. The interference detection module is configured to detect when a power level associated with the interference signal is greater than a threshold value. In one embodiment, the interference detection module generates an interrupt for a processing system when the power level associated with the interference signal is greater than the threshold value.

Claims (63)

1. An integrated circuit comprising:

a sensing arrangement configured to sense an electromagnetic interference signal;

an interference detection module capacitively coupled to the sensing arrangement, wherein the interference detection module is configured to detect when a power level associated with the electromagnetic interference signal is greater than a first threshold value; and

a semiconductor substrate, wherein the sensing arrangement and the interference detection module are formed on the semiconductor substrate and encapsulated in a single device package.

2. The integrated circuit of claim 1 , wherein the sensing arrangement comprises:

a sensing element; and

a capacitive element coupled between the sensing element and the interference detection module.

3. The integrated circuit of claim 2 , wherein the sensing element comprises a conductive trace.

4. The integrated circuit of claim 2 , further comprising a plurality of pins for interfacing with the integrated circuit, wherein the sensing element comprises a first pin of the plurality of pins.

5. The integrated circuit of claim 2 , wherein the sensing element is sensitive to electromagnetic interference.

6. The integrated circuit of claim 1 , wherein the sensing arrangement comprises a first conductive structure overlying the semiconductor substrate and coupled to the interference detection module.

7. The integrated circuit of claim 6 , wherein the sensing arrangement further comprises a dielectric material overlying the semiconductor substrate, wherein the first conductive structure overlies the dielectric material.

8. The integrated circuit of claim 1 , further comprising a leadframe pad affixed to a surface of the semiconductor substrate, wherein the sensing arrangement comprises a capacitive element coupled between the leadframe pad and the interference detection module.

9. An integrated circuit comprising:

a sensing arrangement configured to sense an electromagnetic interference signal; and

an interference detection module coupled to the sensing arrangement, wherein the interference detection module is configured to detect when a power level associated with the electromagnetic interference signal is greater than a first threshold value, wherein the interference detection module comprises:

comparison circuitry coupled to the sensing arrangement, the comparison circuitry being configured to detect when the power level associated with the electromagnetic interference signal is greater than the first threshold value; and

a filtering arrangement coupled to the comparison circuitry, the filtering arrangement being configured to indicate when the power level associated with the electromagnetic interference signal is greater than the first threshold value for a predetermined amount of time.

10. An integrated circuit comprising:

a sensing arrangement configured to sense an electromagnetic interference signal;

an interference detection module coupled to the sensing arrangement, wherein the interference detection module is configured to detect when a power level associated with the electromagnetic interference signal is greater than a first threshold value;

analog circuitry having a bias point, the bias point controlling an operating characteristic of the analog circuitry; and

a voltage regulator coupled to the analog circuitry and the interference detection module, wherein the voltage regulator is configured to adjust the bias point of the analog circuitry when the detected power level of the electromagnetic interference signal is greater than the first threshold value.

11. An integrated circuit comprising:

a sensing arrangement configured to sense an electromagnetic interference signal;

an interference detection module coupled to the sensing arrangement, wherein the interference detection module is configured to detect when a power level associated with the electromagnetic interference signal is greater than a first threshold value; and

a processing system coupled to the interference detection module, wherein:

the interference detection module is configured to generate an interrupt for the processing system when the power level associated with the electromagnetic interference signal is greater than the first threshold value; and

the processing system is configured to take remedial action in response to the interrupt.

12. A method for providing protection from electromagnetic interference in an integrated circuit, the method comprising:

sensing electromagnetic interference within the integrated circuit, resulting in a sensed electromagnetic interference signal;

detecting an interference event based on a power level associated with the sensed electromagnetic interference signal by:

comparing the power level of the sensed electromagnetic interference signal to a first threshold value, and

identifying the interference event when the power level exceeds the first threshold value; and

taking remedial action in response to the interference event.

13. The method of claim 12 , further comprising:

sensing a second electromagnetic interference signal within the integrated circuit, resulting in a second sensed electromagnetic interference signal;

determining a second power level associated with the second sensed electromagnetic interference signal;

comparing the second power level of the second sensed electromagnetic interference signal to a second threshold value, the second threshold value being greater than the first threshold value; and

identifying a second interference event when the second power level exceeds the second threshold value.

14. The method of claim 12 , the integrated circuit including analog circuitry, wherein taking remedial action comprises adjusting a bias point of the analog circuitry in response to the interference event.

15. The method of claim 12 , further comprising generating a first interrupt for a processing system of the integrated circuit in response to the interference event, wherein the processing system is configured to take remedial action in response to the first interrupt.

16. An interference protection system for use with an integrated circuit package, the interference protection system comprising:

a processing system contained in the integrated circuit package;

a sensing arrangement configured to obtain an interference signal in response to electromagnetic interference within the integrated circuit package; and

an interference detection module coupled to the sensing arrangement and the processing system, wherein the interference detection module is configured to:

identify an interference event based on the interference signal; and

generate an interrupt signal for the processing system in response to the interference event, the processing system being configured to take remedial action in response to the interrupt signal.

17. The interference protection system of claim 16 , further comprising a semiconductor substrate, wherein the sensing arrangement comprises:

a conductive trace formed on the semiconductor substrate; and

a capacitive element coupled between the conductive trace and the interference detection module.

18. The interference protection system of claim 16 , further comprising a semiconductor substrate, wherein the sensing arrangement comprises:

a first conductive material overlying the semiconductor substrate, wherein the first conductive material and the semiconductor substrate are electrically connected;

a dielectric material overlying the first conductive material; and

a second conductive material overlying the dielectric material, wherein the second conductive material is coupled to the interference detection module.

19. An integrated circuit comprising:

a processing system;

a sensing arrangement configured to sense an interference signal; and

an interference detection module coupled to the sensing arrangement and the processing system, wherein:

the interference detection module is configured to:

detect when a power level associated with the interference signal is greater than a first threshold value; and

generate an interrupt for the processing system when the power level associated with the interference signal is greater than the first threshold value; and

the processing system is configured to take remedial action in response to the interrupt.

Assignments (25)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037355/0723 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2010
From: OLMOS, ALFREDO; MALTIONE, RICARDO; DA SILVA, EDUARDO RIBERIRO
To: FREESCALE SEMICONDUCTOR, INC.
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