Programmable clock divider
View Patent ↗In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second numbers, respectively, with a count value from a counter to generate first and second signals, respectively. A multiplexer can receive the first and second signals at inputs and can receive the clock signal at a selection input. The multiplexer can output an output signal, as a divided clock signal, based on the clock signal, the first signal, and the second signal, where the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.
1. A clock divider, comprising:
a first circuit, including first logic to perform a first comparison of a first number and a count value to generate a first signal;
a second circuit, including second logic to perform a second comparison of a second number and the count value to generate a second signal; and
a first multiplexer including a first input coupled to the first circuit to receive the first signal, a second input coupled to the second circuit to receive the second signal, a selection input to receive a first clock signal, and an output, wherein the first multiplexer outputs an output signal via the output, as a divided clock signal, based on the first clock signal, the first signal, and the second signal, wherein the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.
2. The clock divider of claim 1 , further comprising:
a second multiplexer including an output coupled to the selection input of the first multiplexer, a first input to receive a second clock signal, and a second input to receive a third clock signal, wherein the output of the second multiplexer provides at least one of the second clock signal and the third clock signal to the selection input of the first multiplexer as the first clock signal, wherein the first multiplexer and the second multiplexer provide a common path for the second clock signal and the third clock signal as an input clock to the clock divider.
3. The clock divider of claim 1 , further comprising:
a counter coupled to the first circuit to provide the count value.
4. The clock divider of claim 3 ,
wherein the second circuit includes:
a logic unit; and
a latch coupled to the logic unit;
wherein the logic unit compares the second number and the count value from the counter and provides the second signal to the latch; and
wherein the latch provides the second signal to the first multiplexer.
5. The clock divider of claim 1 , wherein if the first number is an even number, the output signal transitions from the first value to the second value on the first edge of the first clock signal, and if the first number is an odd number, the output signal transitions from the first value to the second value on the second edge of the first clock signal.
6. The clock divider of claim 1 ,
wherein the first multiplexer receives, from the first circuit, the first value at the first input of the first multiplexer for each of a first set of sequential values corresponding to the second value of the first clock signal;
wherein the first multiplexer receives, from the second circuit, the second value at the second input of the first multiplexer for each of a second set of sequential values corresponding to the first value of the first clock signal;
wherein, if the first number is not equal to the second number, the first multiplexer receives:
the first value, from the second circuit, at the second input of the first multiplexer for each of a third set of sequential values corresponding to the first value of the first clock signal; and
the second value, from the first circuit, at the first input of the first multiplexer for each of a fourth set of sequential values corresponding to the second value of the first clock signal; and
wherein, if the first number is equal to the first number, the first multiplexer receives:
the first value, from the second circuit, at the second input of the first multiplexer for each of a fifth set of sequential values corresponding to the first value the first clock signal; and
the second value, from the first circuit, at the first input of the first multiplexer for each of a sixth set of sequential values corresponding to the second value of the first clock signal.
7. The clock divider of claim 6 , further comprising:
a second multiplexer including an output coupled to the selection input of the first multiplexer, a first input to receive a second clock signal, and a second input to receive a third clock signal, wherein the output of the second multiplexer provides at least one of the second clock signal and the third clock signal to the selection input of the first multiplexer as the first clock signal, wherein the first multiplexer and the second multiplexer provide a common path for the second clock signal and the third clock signal as input clock to the clock divider;
wherein the first multiplexer receives the third clock signal as the first clock signal;
wherein the first multiplexer receives, from the circuit, the first value at the first input of the first multiplexer for each of a seventh set of sequential values corresponding to the second value of the first clock signal;
wherein the first multiplexer receives, from the circuit, the second value at the second input of the first multiplexer for each of an eighth set of sequential values corresponding to the first value of the first clock signal;
wherein, if first number is not equal to the second number, the first multiplexer receives:
the first value, from the second circuit, at the second input of the first multiplexer for each of a ninth set of sequential values corresponding to the first value of the first clock signal; and
the second value, from the circuit, at the first input of the first multiplexer for each of a tenth set of sequential values corresponding to the second value of the first clock signal; and
wherein, if first number equals the second number, the first multiplexer receives:
the first value, from the second circuit, at the second input of the first multiplexer for each of an eleventh set of sequential values corresponding to the first value of the first clock signal; and
the second value, from the circuit, at the first input of the first multiplexer for each of a twelfth set of sequential values corresponding to the second value of the first clock signal.
8. A method of operating a clock divider, comprising:
comparing a first number and a count value;
generating a first signal based on said comparing the first number and the count value;
comparing a second number and the count value;
generating a second signal based on said comparing the second number and the count value;
receiving the first signal at a first input of a first multiplexer;
receiving the second signal at a second input of the first multiplexer;
receiving a first clock signal at a selection input of the first multiplexer;
outputting, as output of the clock divider, an output signal via an output of the first multiplexer, wherein the output signal is based on the first clock signal, the first signal, and the second signal, wherein the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.
9. The method of claim 8 , further comprising:
receiving a second clock signal at a first input of a second multiplexer;
receiving a third clock signal at a second input of the second multiplexer
outputting at least one of the second clock signal and the third clock signal as the first clock signal via an output of the second multiplexer, wherein the output of the second multiplexer is coupled to the selection input of the first multiplexer.
10. The method of claim 9 , wherein the first multiplexer and the second multiplexer provide a common path for the second clock signal and the third clock signal as input clock to the clock divider.
11. The method of claim 8 , further comprising:
adjusting a counter based on the first clock signal; and
providing the count value based on said adjusting the counter.
12. The method of claim 11 , wherein said adjusting the counter includes decrementing the count value.
13. The method of claim 8 ,
wherein said generating the first signal includes:
generating the first value for each of a first set of sequential values corresponding to the second value of the first clock signal;
if the first number is not equal to the second number, generating the second value for each of a second set of sequential values corresponding to the second value of the first clock signal; and
if the first number is equal to the first number, generating the second value for each of a third set of sequential values corresponding to the second value of the first clock signal; and
wherein said generating the second signal includes:
generating the second value for each of a fourth set of sequential values corresponding to the first value of the first clock signal;
if the first number is not equal to the second number, generating the first value for each of a fifth set of sequential values corresponding to the first value of the first clock signal; and
if the first number is equal to the first number, generating the first value for each of a sixth set of sequential values corresponding to the first value the first clock signal.
14. An integrated circuit, comprising:
a first circuit, including first logic to perform a first comparison of a first number and a count value to generate a first signal;
a second circuit, including second logic to perform a second comparison of a second number and the count value to generate a second signal; and
a first multiplexer including a first input coupled to the first circuit to receive the first signal, a second input coupled to the second circuit to receive the second signal, a selection input to receive a first clock signal, and an output, wherein the first multiplexer outputs an output signal via the output, as output of the clock divider, based on the first clock signal, the first signal, and the second signal, wherein the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.
15. The integrated circuit of claim 1 , further comprising:
a second multiplexer including an output coupled to the selection input of the first multiplexer, a first input to receive a second clock signal, and a second input to receive a third clock signal, wherein the output of the second multiplexer provides at least one of the second clock signal and the third clock signal to the selection input of the first multiplexer as the first clock signal, wherein the first multiplexer and the second multiplexer provide a common path for the second clock signal and the third clock signal as input clock to the clock divider.
16. The integrated circuit of claim 15 , further comprising:
a counter coupled to the first circuit to provide the count value;
wherein the first circuit compares the first number and the count value and provides the first signal to the first multiplexer.
17. The integrated circuit of claim 16 ,
wherein the second circuit includes:
a logic unit; and
a latch coupled to the logic unit;
wherein the logic unit compares the second number and the count value from the counter and provides the second signal to the latch; and
wherein the latch provides the second signal to the first multiplexer.
18. The integrated circuit of claim 15 , wherein if the first number is an even number, the output signal transitions from the first value to the second value on the first edge of the first clock signal, and if the first number is an odd number, the output signal transitions from the first value to the second value on the second edge of the first clock signal.
19. The integrated circuit of claim 15 ,
wherein the first multiplexer receives, from the first circuit, the first value at the first input of the first multiplexer for each of a first set of sequential values corresponding to the second value of the first clock signal;
wherein the first multiplexer receives, from the second circuit, the second value at the second input of the first multiplexer for each of a second set of sequential values corresponding to the first value of the first clock signal;
wherein, if the first number is not equal to the second number, the first multiplexer receives:
the first value, from the second circuit, at the second input of the first multiplexer for each of a third set of sequential values corresponding to the first value of the first clock signal; and
the second value, from the first circuit, at the first input of the first multiplexer for each of a fourth set of sequential values corresponding to the second value of the first clock signal; and
wherein, if the first number is equal to the second number, the first multiplexer receives:
the first value, from the second circuit, at the second input of the first multiplexer for each of a fifth set of sequential values corresponding to the first value the first clock signal; and
the second value, from the first circuit, at the first input of the first multiplexer for each of a sixth set of sequential values corresponding to the second value of the first clock signal.
20. The integrated circuit of claim 19 , further comprising:
a second multiplexer including an output coupled to the selection input of the first multiplexer, a first input to receive a second clock signal, and a second input to receive a third clock signal, wherein the output of the second multiplexer provides at least one of the second clock signal and the third clock signal to the selection input of the first multiplexer as the first clock signal, wherein the first multiplexer and the second multiplexer provide a common path for the second clock signal and the third clock signal as input clock to the clock divider;
wherein the first multiplexer receives the third clock signal as the first clock signal;
wherein the first multiplexer receives, from the first circuit, the first value at the first input of the first multiplexer for each of a seventh set of sequential values corresponding to the second value of the first clock signal;
wherein the first multiplexer receives, from the second circuit, the second value at the second input of the first multiplexer for each of an eighth set of sequential values corresponding to the first value of the first clock signal;
wherein, if the first number is not equal to the second number, the first multiplexer receives:
the first value, from the second circuit, at the second input of the first multiplexer for each of a ninth set of sequential values corresponding to the first value of the first clock signal; and
the second value, from the first circuit, at the first input of the first multiplexer for each of a tenth set of sequential values corresponding to the second value of the first clock signal; and
wherein, if first number equals the second number, the first multiplexer receives:
the first value, from the second circuit, at the second input of the first multiplexer for each of an eleventh set of sequential values corresponding to the first value of the first clock signal; and
the second value, from the first circuit, at the first input of the first multiplexer for each of a twelfth set of sequential values corresponding to the second value of the first clock signal.