Dynamic pass voltage for sense operation in a memory device
Methods for sensing and memory devices are disclosed. One such method for sensing uses a dynamic pass voltage on at least one adjacent memory cell that is adjacent to a selected memory cell for programming. If the adjacent memory cell is not programmed, the pass voltage is reduced on the adjacent memory cell. The adjacent memory cell can be on the drain side, the source side, or both drain and source sides of the selected memory cell.
1. A method for sensing a selected memory cell, the method comprising:
biasing the selected memory cell at a sense voltage; and
biasing at least one memory cell, that is adjacent to the selected memory cell, at a pass voltage that is determined responsive to a program status of the at least one adjacent memory cell wherein the pass voltage for the at least one adjacent memory cell is less than a maximum V tn voltage, wherein the n state is a maximum programmable state of the selected memory cell and the pass voltage for the at least one adjacent memory cell is less than the sense voltage for the n state.
2. The method of claim 1 wherein the at least one adjacent memory cell is adjacent to the selected memory cell on a drain side of the selected memory cell in a series string of memory cells.
3. The method of claim 1 wherein the at least one adjacent memory cell is adjacent to the selected memory cell on a source side of the selected memory cell in a series string of memory cells.
4. The method of claim 1 wherein the at least one adjacent memory cell comprises adjacent memory cells on both a source side and a drain side of the selected memory cell in a series string of memory cells.
5. The method of claim 1 wherein if the program status of the at least one adjacent memory cell indicates an erased state, the pass voltage is less than if the program status indicates a programmed state.
6. The method of claim 1 wherein if the program status of the at least one adjacent memory cell indicates that an upper page is programmed, biasing the at least one adjacent memory cell comprises biasing the at least one adjacent memory cell at a higher pass voltage than if the program status indicated that the upper page was not programmed.
7. The method of claim 1 wherein if the program status of the at least one adjacent memory cell indicates that an upper page is not programmed, biasing the at least adjacent memory cell comprises biasing the at least one adjacent memory cell at a lower pass voltage than if the program status indicated that the upper page was programmed.
8. A method for sensing a selected memory cell, the method comprising:
biasing the selected memory cell at a sense voltage; and
biasing at least one memory cell, that is adjacent to the selected memory cell, at a pass voltage that is determined responsive to a program status of the at least one adjacent memory cell wherein the pass voltage for the adjacent memory cell is greater than a reference voltage used in determining the program status of the at least one adjacent memory cell.
9. A method for sensing a selected memory cell, the method comprising:
determining a program status of a memory cell adjacent to the selected memory cell prior to sensing the selected memory cell;
biasing the selected memory cell with a sense voltage; and
biasing the adjacent memory cell with a pass voltage responsive to the program status of the adjacent memory cell wherein the pass voltage includes a range of voltages that include a high pass voltage that is greater than the pass voltage, a maximum threshold voltage for an n state that is less than the high pass voltage, and a program verify voltage for the n state that is less than the maximum threshold voltage wherein the n state is a highest programmable state of the selected memory cell.
10. The method of claim 9 wherein the selected memory cell is a single level cell configured to store a single bit of data.
11. The method of claim 9 wherein the selected memory cell is a multiple level cell configured to store a plurality of bits of data.
12. The method of claim 9 wherein the sensing is a memory read operation.
13. The method of claim 9 wherein the sensing is a program verify operation and the sense voltage is a program verify voltage.
14. The method of claim 9 wherein the selected memory cell is coupled to access line WL n and the adjacent memory cell is coupled to access line WL n+1 and the selected memory cell and adjacent memory cell are biased in response to biasing of the WL n and WL n+1 access lines.
15. The method of claim 14 wherein the adjacent memory cell comprises a memory cell coupled to the WL n+1 access line and a memory cell coupled to the WL n−1 access line.
16. The method of claim 9 wherein the pass voltage is higher for program status of programmed than of programmed status of not programmed.
17. The method of claim 16 wherein determining a program status comprises biasing the adjacent memory cells with a reference voltage.
18. The method of claim 9 wherein the program status is one of an absolute threshold voltage or an upper page program status.
19. A method for sensing a selected memory cell, the method comprising:
determining, using a reference voltage, whether the upper page of a memory cell adjacent to a selected memory cell is programmed;
if an upper page of the adjacent memory cell is not programmed, performing the sensing of the selected memory cell while biasing the adjacent memory cell with a first voltage; and
if the upper page of the adjacent memory cell is programmed, performing the sensing of the selected memory cell while biasing the adjacent memory cell with a second voltage;
wherein the first and second voltages are greater than the reference voltage.
20. The method of claim 19 wherein the second voltage is greater than the first voltage.
21. The method of claim 20 wherein biasing the adjacent memory cell comprises:
sequentially biasing the adjacent memory cell at the first voltage then the second voltage during a sensing operation.
22. A memory device comprising:
a memory array comprising a plurality of memory cells configured into series strings of memory cells; and
control circuitry coupled to the memory array and configured to bias a control gate of at least one memory cell that is adjacent to a memory cell selected for sensing with a first pass voltage when the at least one adjacent memory cell is not programmed and with a second pass voltage when the at least one adjacent memory cell is programmed, wherein the first pass voltage is lower than the second pass voltage and further wherein the first pass voltage and the second pass voltage are greater than a reference voltage used in determining if the at least one memory cell that is adjacent to the memory cell selected for sensing is programmed.
23. The memory device of claim 22 wherein the memory array is comprised of a NAND architecture.
24. The memory device of claim 22 wherein the at least one adjacent memory cell comprises a first memory cell on a drain side of the selected memory cell and a second memory cell on a source side of the selected memory cell.
25. The memory system of claim 22 wherein the first pass voltage and the second pass voltage are such that an effective channel length under the selected memory cell is substantially the same regardless of whether the adjacent memory cell is programmed.
26. The memory system of claim 22 wherein the control circuitry is further configured to determine a program status of the adjacent memory cell prior to the sense operation and bias the adjacent memory cell with the first pass voltage or the second pass voltage responsive to the determined program status.
27. A method for sensing a selected memory cell of a string of memory cells, the method comprising:
biasing the selected memory cell with a program verify voltage;
biasing only a memory cell adjacent to the selected memory cell with a low pass voltage; and
biasing remaining memory cells of the string of memory cells with a high pass voltage that is greater than the low pass voltage wherein the low pass voltage is less than a maximum threshold voltage for an n state of the selected memory cell wherein the n state is a maximum programmable state for the selected memory cell.
28. A method for sensing a selected memory cell of a string of memory cells, the method comprising:
biasing the selected memory cell with a program verify voltage;
biasing only a memory cell adjacent to the selected memory cell with a low pass voltage; and
biasing remaining memory cells of the string of memory cells with a high pass voltage that is greater than the low pass voltage wherein the low pass voltage is less than the program verify voltage.
29. The method of claim 28 wherein the adjacent memory cell has not yet been programmed to a maximum programmable state.