Method for forming inlaid interconnect
View Patent ↗After a groove is formed in an insulating layer formed on a semiconductor substrate, a barrier metal layer is formed on the insulating layer by an ALD process so as to cover the side walls and bottom of the groove, and an impurity layer is formed in or on the surface of the barrier metal layer by an ion implantation process or by an ALD process. Thereafter, the barrier metal layer and the impurity layer are alloyed, and then an inlaid interconnect layer, which is composed of a Cu seed layer and a Cu plating layer, is formed in the groove. Then, an impurity element in the alloyed barrier metal layer is thermally diffused into the inlaid interconnect layer.
1. A method for forming an inlaid interconnect, comprising the steps of:
(a) forming a groove for an interconnect in an insulating layer formed on a semiconductor substrate;
(b) forming an impurity layer containing an impurity element on the insulating layer by an atomic layer deposition process so as to cover side walls and a bottom of the groove;
(c) forming a barrier metal layer on a surface of the impurity layer by an atomic layer deposition process;
(d) alloying the impurity layer and the barrier metal layer;
(e) forming a Cu seed layer on the alloyed barrier metal layer and then forming a Cu plating layer so as to fill the groove;
(f) removing part of the Cu plating layer, part of the Cu seed layer, and part of the alloyed barrier metal layer located on the insulating layer so as to expose a surface of the insulating layer, thereby forming, in the groove, an inlaid interconnect layer including the Cu seed layer and the Cu plating layer; and
(g) causing thermal diffusion of the impurity element existing in the alloyed barrier metal layer into the inlaid interconnect layer.
2. The method of claim 1 , wherein in the step (g), the impurity element diffused into the inlaid interconnect layer is distributed at a higher concentration near an interface between the impurity layer and the inlaid interconnect layer than in an inner part of the inlaid interconnect layer.
3. The method of claim 1 , wherein the step (e) further includes the step of alloying the impurity layer and the Cu seed layer.
4. The method of claim 1 , wherein the impurity element is aluminum, nickel, or cobalt.
5. The method of claim 1 , wherein the impurity layer has a thickness of from 0.1 to 10 nm.