Method of forming an insulated gate field effect transistor device having a shield electrode structure

1. A method of forming a semiconductor device comprising the steps of:

providing a semiconductor substrate having a major surface;

forming a dielectric stack overlying the major surface, wherein the dielectric stack comprises at least two layers of different material, and wherein the dielectric stack has a first surface;

forming first openings in the dielectric stack;

forming trenches in the semiconductor substrate through the first openings to a first depth;

forming insulated shield electrodes in lower portions of the trenches;

forming insulated gate electrodes in the trenches above the insulated shield electrodes, wherein the insulated gate electrodes comprise a conductive gate material having upper surfaces in proximity to the first surface;

removing at least portions of the dielectric stack thereby leaving portions of the conductive gate material extending above the major surface;

forming first spacers adjacent to the portions of the conductive gate material, wherein segments of the major surface are exposed between adjacent trenches;

removing portions of conductive gate material and portions of the semiconductor substrate self-aligned to the first spacers, wherein the removing step forms first recessed portions overlying the conductive gate material, and second recessed portions within the semiconductor substrate;

forming second spacers in the first and second recessed portions;

forming enhancement regions in the first and second recessed portions self-aligned to the second spacers;

forming insulating regions overlying the first recessed portions; and

forming a first conductive layer coupled to the semiconductor substrate through the second recessed portions.

2. The method of claim 1 , wherein the step of forming the insulated shield electrodes comprises the steps of:

forming a first dielectric layer overlying surfaces of the trenches, wherein the first dielectric layer has a first thickness;

forming a second dielectric layer overlying the first dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise different materials;

forming second openings along lower portions of the trenches through the first and second dielectric layers;

forming the trenches to a second depth greater than the first depth through the second openings to form shield electrode trench portions;

forming a third dielectric layer along surfaces of the shield electrode trench portions, wherein the third dielectric layer has a second thickness;

forming shield electrodes overlying the third dielectric layer, wherein the shield electrodes are recessed within the trenches; and

forming a fourth dielectric layer overlying the shield electrodes.

3. The method of claim 2 , wherein the step of forming the third dielectric layer includes forming the third dielectric layer, wherein the second thickness is greater than the first thickness.

4. The method of claim 2 , wherein the step of forming the first dielectric layer includes forming an oxide layer, and wherein the step of forming the second dielectric comprises forming a nitride layer.

5. The method of claim 2 , wherein the step of forming the insulated gate electrodes comprises the steps of:

removing remaining portions of the second dielectric layer after the step of forming the fourth dielectric layer; and

forming the gate conductive material overlying the fourth and first dielectric layers.

6. The method of claim 2 , wherein the step of forming the shield electrodes includes forming the shield electrodes comprising polysilicon and a silicide.

7. The method of claim 6 , wherein the step of forming the shield electrodes includes forming the shield electrodes, wherein the polysilicon surrounds the silicide.

8. The method of claim 2 , wherein the step of forming the shield electrodes includes forming the shield electrodes comprising a metal.

9. The method of claim 2 further comprising the step of forming a polysilicon layer overlying the first dielectric layer before the step of forming the second dielectric layer.

10. The method of claim 1 , wherein the step of forming the enhancement regions including forming silicide regions.

11. The method of claim 1 , wherein the step of forming the dielectric stack comprises the steps of:

forming a first layer comprising an oxide; and

forming a second layer comprising a nitride overlying the first layer.

12. The method of claim 1 , wherein the step of providing the semiconductor substrate includes providing a semiconductor substrate comprising a first conductivity type, and wherein the method further comprises the step of forming a body region within the semiconductor substrate, wherein the body region and the insulated gate electrodes are adjacent, and wherein the body region comprises a second conductivity type opposite to the first conductivity type.

13. The method of claim 12 , wherein the body region is formed prior the step of forming the trenches.

14. The method of claim 12 , wherein the body region is formed after the step of forming the trenches.

15. The method of claim 1 , wherein the step of forming the first conductive layer includes forming conductive plug regions.

16. The method of claim 1 , wherein the step of removing at least portions of the dielectric stack includes the steps of:

removing all of the dielectric stack; and

exposing conductive gate material above the major surface.

17. A method for forming a semiconductor device comprising the steps of:

providing a semiconductor substrate having a major surface, a pair of adjacent trenches, and a dielectric stack overlying the major surface between the pair of adjacent trenches, wherein each trench includes an insulated gate electrode portion including a gate electrode layer formed with first surface in proximity to an upper surface of the dielectric stack;

removing the dielectric stack along side surfaces of the insulated gate electrode above the major surface;

forming first spacers adjacent the side surfaces;

removing a portion of the gate electrode layer adjacent the first spacers to form a first recessed portion;

removing a portion of the semiconductor substrate to form a second recessed portion self-aligned to the first spacers; and

forming enhancement regions within the first and second recessed portions.

18. The method of claim 17 , wherein the step of providing the semiconductor substrate further includes providing a semiconductor substrate of a first conductivity type with a body region of a second conductivity type formed between adjacent trenches and source regions formed within the body region, the method of forming the enhancement regions includes forming the enhancement regions along side surfaces of the second recessed portions adjoining the source regions.

19. The method of claim 17 further comprising the step of forming second spacers within the first and second recessed portions before the step of forming the enhancement regions, and wherein the step of forming the enhancement regions includes forming the enhancement regions self-aligned to the second spacers.

20. The method of claim 17 , wherein the step of providing the semiconductor substrate includes providing a semiconductor substrate, wherein each trench includes an insulated shield electrode portion underlying the insulated gate electrode portion.

21. A method for forming a semiconductor device comprising the steps of:

providing a semiconductor substrate having a major surface, a pair of adjacent trenches, and a dielectric stack overlying the major surface between the pair of adjacent trenches, wherein each trench includes an insulated gate electrode portion including a gate electrode layer and an insulated shield electrode portion underlying the insulated gate electrode portion;

removing the dielectric stack along side surfaces of the insulated gate electrode above the major surface;

forming first spacers adjacent the side surfaces;

removing a portion of the gate electrode layer adjacent the first spacers to form a first recessed portion;

removing a portion of the semiconductor substrate to form a second recessed portion self-aligned to the first spacers;

forming second spacers within the first and second recessed portions and

forming enhancement regions within the first and second recessed portions self-aligned to the second spacers.

22. The method of claim 21 , wherein the step of providing the semiconductor substrate includes providing the semiconductor substrate, wherein at least one insulated shield electrode portion has a wider lateral dimension than that of at least one insulated gate electrode portion.