IP Library Granted Patent US 7,965,046
Granted Patent B2
US 7,965,046 · App. 12/638,889 · Granted Jun 21, 2011

Full-bridge and half-bridge compatible driver timing schedule for direct drive backlight system

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Quick Facts
Patent No.
US 7,965,046
App. No.
12/638,889
Filed
Dec 15, 2009
Granted
Jun 21, 2011
Kind
B2
Art Unit
2821
USPC
315/224
Abstract

A driver circuit or controller flexibly drives either a half-bridge or a full-bridge switching network in a backlight inverter without modification, redundant circuitry or additional components. The driver circuit includes four outputs to provide four respective driving signals that establish a periodic timing sequence using a zero-voltage switching technique for semiconductor switches in the switching network.

Claims (29)

1. A method to flexibly control a half-bridge or a full-bridge switching network in a backlight inverter, the method comprising generating at least four driving signals with alternating states to control the switching network, wherein the first and the second driving signals are substantially identical with an 180° phase shift, the third and the fourth driving signals have rising edges that precede respective rising edges of the first and the second driving signals by a first duration, and the third and the fourth driving signals have falling edges that trail respective falling edges of the first and the second driving signals by a second duration.

2. The method of claim 1 , wherein the driving signals are generated using a pair of input signals and four delay circuits.

3. The method of claim 2 , wherein the half-bridge network comprises two semiconductor switches and the first and the second driving signals control the two semiconductor switches.

4. The method of claim 3 , wherein the full-bridge network comprises four semiconductor switches, the first and the fourth driving signals control the two semiconductor switches that complete a first conduction path to deliver power to a load, and the second and the third driving signals control the two semiconductor switches that complete a second conduction path to deliver power to the load.

5. The method of claim 4 , further comprising driving a transformer with the semiconductor switches wherein the semiconductor switches are coupled to a primary winding of the transformer and the load is coupled to a secondary winding of the transformer.

6. The method of claim 5 , wherein a secondary winding of the transformer powers a load comprising at least one cold cathode fluorescent lamp that backlights a liquid crystal display.

7. The method of claim 1 , wherein four delay circuits generate the first, second, third and fourth driving signals.

8. The method of claim 1 , wherein the first driving signal and the second driving signal have variable and substantially identical duty cycles.

9. The method of claim 1 , further comprising:

coupling a direct current source to a center tap of a primary winding of a transformer; and

controlling a first N-type field-effect-transistor with first driving signal wherein a first N-type field-effect-transistor is coupled between circuit ground and a first terminal of the primary winding of the transformer; and

controlling a second N-type field-effect-transistor with the second driving signal, wherein the second N-type field-effect-transistor is coupled between circuit ground and a second terminal of the primary winding of the transformer.

10. The method of claim 1 , wherein the first driving signal and the third driving signal are generated from a first input signal using two delay circuits, the second driving signal and the fourth driving signal are generated from a second input signal using another two delay circuits.

11. A method to flexibly control a half-bridge or a full-bridge switching network in a backlight inverter, the method comprising:

generating first and the second driving signals are substantially identical with a 180° phase shift;

generating third and the fourth driving signals have rising edges that precede respective rising edges of the first and the second driving signals by a first duration, and wherein the third and the fourth driving signals have falling edges that trail respective falling edges of the first and the second driving signals by a second duration; and

driving a switching network comprising a plurality of semiconductor switches with the first, second, third and fourth driving signals to convert a direct current source into an alternating current source to power a load.

12. The method of claim 11 , wherein the driving signals are generated using a pair of input signals and four delay circuits.

13. The method of claim 12 , wherein the switching network comprises two semiconductor switches and the first and the second driving signals control the two semiconductor switches.

14. The method of claim 13 , wherein the switching network comprises four semiconductor switches, the first and the fourth driving signals control the two semiconductor switches that complete a first conduction path to deliver power to the load, and the second and the third driving signals control the two semiconductor switches that complete a second conduction path to deliver power to the load.

15. The method of claim 14 , further comprising driving a transformer with the semiconductor switches wherein the semiconductor switches are coupled to a primary winding of the transformer and the load is coupled to a secondary winding of the transformer.

16. The method of claim 15 , wherein a secondary winding of the transformer powers a load comprising at least one cold cathode fluorescent lamp that backlights a liquid crystal display.

17. The method of claim 11 , wherein four delay circuits generate the first, second, third and fourth driving signals.

18. The method of claim 11 , wherein the first driving signal and the second driving signal have variable and substantially identical duty cycles.

19. The method of claim 1 , further comprising:

coupling a direct current source to a center tap of a primary winding of a transformer; and

controlling a first N-type field-effect-transistor with first driving signal wherein a first N-type field-effect-transistor is coupled between circuit ground and a first terminal of the primary winding of the transformer; and

controlling a second N-type field-effect-transistor with the second driving signal, wherein the second N-type field-effect-transistor is coupled between circuit ground and a second terminal of the primary winding of the transformer.

20. The method of claim 1 , wherein the first driving signal and the third driving signal are generated from a first input signal using two delay circuits, the second driving signal and the fourth driving signal are generated from a second input signal using another two delay circuits.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
NOTICE OF SUCCESSION OF AGENCY Recorded Apr 9, 2015
From: ROYAL BANK OF CANADA (AS SUCCESSOR TO MORGAN STANLEY & CO. LLC)
To: BANK OF AMERICA, N.A., AS SUCCESSOR AGENT
Reel/Frame 035657/0223 →
SUPPLEMENTAL PATENT SECURITY AGREEMENT Recorded Nov 11, 2011
From: MICROSEMI CORPORATION; MICROSEMI CORP. - ANALOG MIXED SIGNAL GROUP; MICROSEMI CORP. - MASSACHUSETTS; ACTEL CORPORATION
To: MORGAN STANLEY & CO. LLC
Reel/Frame 027213/0611 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2011
From: WHITE ELECTRONIC DESIGNS CORP.; ACTEL CORPORATION; MICROSEMI CORPORATION
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 025783/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2009
From: CHIOU, CHII-FA
To: MICROSEUMI CORPORATION
Reel/Frame 023658/0578 →